{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1747363868996 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1747363868996 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 16 10:51:08 2025 " "Processing started: Fri May 16 10:51:08 2025" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1747363868996 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363868996 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off general_project -c general_project " "Command: quartus_map --read_settings_files=on --write_settings_files=off general_project -c general_project" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363868996 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1747363869456 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1747363869456 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "start START tx.v(7) " "Verilog HDL Declaration information at tx.v(7): object \"start\" differs only in case from object \"START\" in the same scope" {  } { { "../rtl/tx.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tx.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747363877066 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx " "Found entity 1: tx" {  } { { "../rtl/tx.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tx.v" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877066 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877066 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/tube_ctl.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/tube_ctl.v" { { "Info" "ISGN_ENTITY_NAME" "1 tube_ctl " "Found entity 1: tube_ctl" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877066 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877066 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx " "Found entity 1: rx" {  } { { "../rtl/rx.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/rx.v" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877066 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877066 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(51) " "Verilog HDL Expression warning at num_tran.v(51): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 51 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(52) " "Verilog HDL Expression warning at num_tran.v(52): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 52 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(53) " "Verilog HDL Expression warning at num_tran.v(53): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 53 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(54) " "Verilog HDL Expression warning at num_tran.v(54): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 54 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(55) " "Verilog HDL Expression warning at num_tran.v(55): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 55 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(56) " "Verilog HDL Expression warning at num_tran.v(56): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 56 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/num_tran.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/num_tran.v" { { "Info" "ISGN_ENTITY_NAME" "1 num_tran " "Found entity 1: num_tran" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877080 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/led_tube.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/led_tube.v" { { "Info" "ISGN_ENTITY_NAME" "1 LED_tube " "Found entity 1: LED_tube" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877080 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "5 LED_matrix.v(28) " "Verilog HDL Expression warning at LED_matrix.v(28): truncated literal to match 5 bits" {  } { { "../rtl/LED_matrix.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v" 28 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/led_matrix.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/led_matrix.v" { { "Info" "ISGN_ENTITY_NAME" "1 LED_matrix " "Found entity 1: LED_matrix" {  } { { "../rtl/LED_matrix.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877080 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/key_filter.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/key_filter.v" { { "Info" "ISGN_ENTITY_NAME" "1 key_filter " "Found entity 1: key_filter" {  } { { "../rtl/key_filter.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/key_filter.v" 20 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877080 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877080 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/general_project.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/general_project.v" { { "Info" "ISGN_ENTITY_NAME" "1 general_project " "Found entity 1: general_project" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877096 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877096 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "general_project " "Elaborating entity \"general_project\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1747363877194 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 general_project.v(40) " "Verilog HDL assignment warning at general_project.v(40): truncated value with size 32 to match size of target (20)" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877194 "|general_project"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "led general_project.v(16) " "Output port \"led\" at general_project.v(16) has no driver" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1747363877194 "|general_project"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "tx_G1 general_project.v(6) " "Output port \"tx_G1\" at general_project.v(6) has no driver" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1747363877194 "|general_project"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED_tube LED_tube:LED_tube_1 " "Elaborating entity \"LED_tube\" for hierarchy \"LED_tube:LED_tube_1\"" {  } { { "../rtl/general_project.v" "LED_tube_1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 76 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 LED_tube.v(26) " "Verilog HDL assignment warning at LED_tube.v(26): truncated value with size 32 to match size of target (8)" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_tube:LED_tube_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 LED_tube.v(30) " "Verilog HDL assignment warning at LED_tube.v(30): truncated value with size 32 to match size of target (8)" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_tube:LED_tube_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 LED_tube.v(33) " "Verilog HDL assignment warning at LED_tube.v(33): truncated value with size 32 to match size of target (8)" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_tube:LED_tube_1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "num_tran LED_tube:LED_tube_1\|num_tran:num_tran_1 " "Elaborating entity \"num_tran\" for hierarchy \"LED_tube:LED_tube_1\|num_tran:num_tran_1\"" {  } { { "../rtl/LED_tube.v" "num_tran_1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 52 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(18) " "Verilog HDL assignment warning at num_tran.v(18): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(19) " "Verilog HDL assignment warning at num_tran.v(19): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(20) " "Verilog HDL assignment warning at num_tran.v(20): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(21) " "Verilog HDL assignment warning at num_tran.v(21): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(22) " "Verilog HDL assignment warning at num_tran.v(22): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(23) " "Verilog HDL assignment warning at num_tran.v(23): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tube_ctl LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1 " "Elaborating entity \"tube_ctl\" for hierarchy \"LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\"" {  } { { "../rtl/LED_tube.v" "tube_ctl_1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 62 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED_matrix LED_matrix:LED_matrix_1 " "Elaborating entity \"LED_matrix\" for hierarchy \"LED_matrix:LED_matrix_1\"" {  } { { "../rtl/general_project.v" "LED_matrix_1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 84 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 LED_matrix.v(15) " "Verilog HDL assignment warning at LED_matrix.v(15): truncated value with size 32 to match size of target (16)" {  } { { "../rtl/LED_matrix.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_matrix:LED_matrix_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 LED_matrix.v(17) " "Verilog HDL assignment warning at LED_matrix.v(17): truncated value with size 32 to match size of target (6)" {  } { { "../rtl/LED_matrix.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 "|general_project|LED_matrix:LED_matrix_1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key_filter key_filter:key_filter_1 " "Elaborating entity \"key_filter\" for hierarchy \"key_filter:key_filter_1\"" {  } { { "../rtl/general_project.v" "key_filter_1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 93 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877208 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "13 " "Inferred 13 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|Div0\"" {  } { { "../rtl/LED_tube.v" "Div0" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 26 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div2\"" {  } { { "../rtl/num_tran.v" "Div2" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod5 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod5\"" {  } { { "../rtl/num_tran.v" "Mod5" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod4 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod4\"" {  } { { "../rtl/num_tran.v" "Mod4" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 22 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|Mod0\"" {  } { { "../rtl/LED_tube.v" "Mod0" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|Div1\"" {  } { { "../rtl/LED_tube.v" "Div1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div1\"" {  } { { "../rtl/num_tran.v" "Div1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 21 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod3 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod3\"" {  } { { "../rtl/num_tran.v" "Mod3" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 21 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod2\"" {  } { { "../rtl/num_tran.v" "Mod2" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 20 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|Mod1\"" {  } { { "../rtl/LED_tube.v" "Mod1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 33 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div0\"" {  } { { "../rtl/num_tran.v" "Div0" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod1\"" {  } { { "../rtl/num_tran.v" "Mod1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod0\"" {  } { { "../rtl/num_tran.v" "Mod0" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 18 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363877466 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1747363877466 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|lpm_divide:Div0\"" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 26 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877507 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|lpm_divide:Div0 " "Instantiated megafunction \"LED_tube:LED_tube_1\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 20 " "Parameter \"LPM_WIDTHN\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877507 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 14 " "Parameter \"LPM_WIDTHD\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877507 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877507 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877507 ""}  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 26 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363877507 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ekm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ekm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ekm " "Found entity 1: lpm_divide_ekm" {  } { { "db/lpm_divide_ekm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_ekm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877544 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877544 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_6nh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_6nh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_6nh " "Found entity 1: sign_div_unsign_6nh" {  } { { "db/sign_div_unsign_6nh.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_6nh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877560 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877560 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_0af.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_0af.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_0af " "Found entity 1: alt_u_div_0af" {  } { { "db/alt_u_div_0af.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_0af.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877592 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877592 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7pc " "Found entity 1: add_sub_7pc" {  } { { "db/add_sub_7pc.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/add_sub_7pc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877643 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877643 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8pc " "Found entity 1: add_sub_8pc" {  } { { "db/add_sub_8pc.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/add_sub_8pc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877691 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877691 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div2 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div2\"" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877705 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div2 " "Instantiated megafunction \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877705 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877705 ""}  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363877705 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_jhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_jhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_jhm " "Found entity 1: lpm_divide_jhm" {  } { { "db/lpm_divide_jhm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_jhm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877737 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877737 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_bkh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_bkh " "Found entity 1: sign_div_unsign_bkh" {  } { { "db/sign_div_unsign_bkh.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_bkh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877753 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877753 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_a4f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_a4f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_a4f " "Found entity 1: alt_u_div_a4f" {  } { { "db/alt_u_div_a4f.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877771 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877771 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5\"" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877787 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5 " "Instantiated megafunction \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877787 ""}  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363877787 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_m9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_m9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_m9m " "Found entity 1: lpm_divide_m9m" {  } { { "db/lpm_divide_m9m.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_m9m.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877835 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877835 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|lpm_divide:Mod0\"" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877865 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|lpm_divide:Mod0 " "Instantiated megafunction \"LED_tube:LED_tube_1\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 20 " "Parameter \"LPM_WIDTHN\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877865 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 14 " "Parameter \"LPM_WIDTHD\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877865 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877865 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877865 ""}  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363877865 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_hcm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_hcm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_hcm " "Found entity 1: lpm_divide_hcm" {  } { { "db/lpm_divide_hcm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_hcm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877898 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877898 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|lpm_divide:Div1\"" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363877912 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|lpm_divide:Div1 " "Instantiated megafunction \"LED_tube:LED_tube_1\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 14 " "Parameter \"LPM_WIDTHN\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877912 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 7 " "Parameter \"LPM_WIDTHD\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877912 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877912 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363877912 ""}  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363877912 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_3jm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_3jm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_3jm " "Found entity 1: lpm_divide_3jm" {  } { { "db/lpm_divide_3jm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_3jm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877962 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877962 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_rlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_rlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_rlh " "Found entity 1: sign_div_unsign_rlh" {  } { { "db/sign_div_unsign_rlh.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_rlh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363877982 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363877982 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_a7f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_a7f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_a7f " "Found entity 1: alt_u_div_a7f" {  } { { "db/alt_u_div_a7f.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a7f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363878010 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363878010 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|lpm_divide:Mod1 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|lpm_divide:Mod1\"" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 33 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363878055 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|lpm_divide:Mod1 " "Instantiated megafunction \"LED_tube:LED_tube_1\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 20 " "Parameter \"LPM_WIDTHN\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878055 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 7 " "Parameter \"LPM_WIDTHD\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878055 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878055 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878055 ""}  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 33 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363878055 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_3bm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_3bm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_3bm " "Found entity 1: lpm_divide_3bm" {  } { { "db/lpm_divide_3bm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_3bm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363878103 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363878103 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_olh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_olh " "Found entity 1: sign_div_unsign_olh" {  } { { "db/sign_div_unsign_olh.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_olh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363878119 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363878119 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_47f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_47f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_47f " "Found entity 1: alt_u_div_47f" {  } { { "db/alt_u_div_47f.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_47f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363878152 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363878152 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div0\"" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363878174 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div0 " "Instantiated megafunction \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878174 ""}  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363878174 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod0\"" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 18 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363878198 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod0 " "Instantiated megafunction \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363878198 ""}  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 18 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363878198 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 73 -1 0 } } { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 59 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1747363878471 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1747363878471 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "tx_G1 GND " "Pin \"tx_G1\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363879368 "|general_project|tx_G1"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[0\] GND " "Pin \"led\[0\]\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363879368 "|general_project|led[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[1\] GND " "Pin \"led\[1\]\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363879368 "|general_project|led[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[2\] GND " "Pin \"led\[2\]\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363879368 "|general_project|led[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[3\] GND " "Pin \"led\[3\]\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363879368 "|general_project|led[3]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1747363879368 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1747363879440 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1747363879945 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5\|lpm_divide_m9m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_a4f:divider\|add_sub_7_result_int\[0\]~0 " "Logic cell \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5\|lpm_divide_m9m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_a4f:divider\|add_sub_7_result_int\[0\]~0\"" {  } { { "db/alt_u_div_a4f.tdf" "add_sub_7_result_int\[0\]~0" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf" 61 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363879951 ""} { "Info" "ISCL_SCL_CELL_NAME" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_a4f:divider\|add_sub_7_result_int\[0\]~0 " "Logic cell \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_a4f:divider\|add_sub_7_result_int\[0\]~0\"" {  } { { "db/alt_u_div_a4f.tdf" "add_sub_7_result_int\[0\]~0" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf" 61 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363879951 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1747363879951 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.map.smsg " "Generated suppressed messages file C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363879982 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1747363880112 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363880112 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_M2 " "No output dependent on input pin \"rx_M2\"" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 5 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363880211 "|general_project|rx_M2"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1747363880211 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1666 " "Implemented 1666 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1747363880211 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1747363880211 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1642 " "Implemented 1642 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1747363880211 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1747363880211 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 30 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4867 " "Peak virtual memory: 4867 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1747363880222 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 16 10:51:20 2025 " "Processing ended: Fri May 16 10:51:20 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1747363880222 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1747363880222 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1747363880222 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363880222 ""}
