module num_tran (
    input wire clk,
    input wire rst_n,
    input wire [7:0] numin_1,
    input wire [7:0] numin_2,
    input wire [7:0] numin_3,

    output reg  [47:0] num_display
);

wire [3:0] num_1;
wire [3:0] num_2;
wire [3:0] num_3;
wire [3:0] num_4;
wire [3:0] num_5;
wire [3:0] num_6;
// 两位数 ---> 一位数
assign num_1 = numin_1 % 10;
assign num_2 = (numin_1 / 10) % 10;
assign num_3 = numin_2 % 10;
assign num_4 = (numin_2 / 10) % 10;
assign num_5 = numin_3 % 10;
assign num_6 = (numin_3 / 10) % 10;

// 译码
function [7:0] num_decode;
    input [3:0] num_oringnal;
    case (num_oringnal)
        4'h0: num_decode = 8'hC0;
        4'h1: num_decode = 8'hF9;
        4'h2: num_decode = 8'hA4;
        4'h3: num_decode = 8'hB0;
        4'h4: num_decode = 8'h99;
        4'h5: num_decode = 8'h92;
        4'h6: num_decode = 8'h82;
        4'h7: num_decode = 8'hF8;
        4'h8: num_decode = 8'h80;
        4'h9: num_decode = 8'h90;
        default: num_decode = 8'hFF;        
    endcase
endfunction

reg [7:0] num_decode_1;
reg [7:0] num_decode_2;
reg [7:0] num_decode_3;
reg [7:0] num_decode_4;
reg [7:0] num_decode_5;
reg [7:0] num_decode_6;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        num_decode_1 <= 4'hff;
        num_decode_2 <= 4'hff;
        num_decode_3 <= 4'hff;
        num_decode_4 <= 4'hff;
        num_decode_5 <= 4'hff;
        num_decode_6 <= 4'hff; 
    end
    else begin
        num_decode_1 <= num_decode(num_1);
        num_decode_2 <= num_decode(num_2);
        num_decode_3 <= num_decode(num_3);
        num_decode_4 <= num_decode(num_4);
        num_decode_5 <= num_decode(num_5);
        num_decode_6 <= num_decode(num_6);         
    end
end

// 字符拼接
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        num_display <= 48'hFFFF_FFFF_FFFF;
    else
        num_display <= {num_decode_6, num_decode_5, num_decode_4,
                        num_decode_3, num_decode_2, num_decode_1};
end

endmodule