# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 09:24:51  May 07, 2025
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		general_project_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6F17C8
set_global_assignment -name TOP_LEVEL_ENTITY general_project
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:24:51  MAY 07, 2025"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_A5 -to DIG[7]
set_location_assignment PIN_B8 -to DIG[6]
set_location_assignment PIN_A7 -to DIG[5]
set_location_assignment PIN_B6 -to DIG[4]
set_location_assignment PIN_B5 -to DIG[3]
set_location_assignment PIN_A6 -to DIG[2]
set_location_assignment PIN_A8 -to DIG[1]
set_location_assignment PIN_B7 -to DIG[0]
set_location_assignment PIN_B1 -to SEL[5]
set_location_assignment PIN_A2 -to SEL[4]
set_location_assignment PIN_B3 -to SEL[3]
set_location_assignment PIN_A3 -to SEL[2]
set_location_assignment PIN_B4 -to SEL[1]
set_location_assignment PIN_A4 -to SEL[0]
set_location_assignment PIN_E1 -to clk
set_location_assignment PIN_E15 -to rst_n
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIG[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIG[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIG[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIG[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIG[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIG[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIG[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIG[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SEL[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SEL[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SEL[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SEL[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SEL[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SEL[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to led[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to led[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to led[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to led[0]
set_location_assignment PIN_D16 -to led[3]
set_location_assignment PIN_F15 -to led[2]
set_location_assignment PIN_F16 -to led[1]
set_location_assignment PIN_G15 -to led[0]
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VERILOG_FILE ../rtl/tx.v
set_global_assignment -name VERILOG_FILE ../rtl/tube_ctl.v
set_global_assignment -name VERILOG_FILE ../rtl/rx.v
set_global_assignment -name VERILOG_FILE ../rtl/num_tran.v
set_global_assignment -name VERILOG_FILE ../rtl/LED_tube.v
set_global_assignment -name VERILOG_FILE ../rtl/LED_matrix.v
set_global_assignment -name VERILOG_FILE ../rtl/key_filter.v
set_global_assignment -name VERILOG_FILE ../rtl/general_project.v
set_location_assignment PIN_F8 -to key_F8
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to key_F8
set_location_assignment PIN_M2 -to rx_M2
set_location_assignment PIN_G1 -to tx_G1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to tx_G1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rx_M2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to matrix_K6
set_location_assignment PIN_K6 -to matrix_K6
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top