{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1747363881583 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1747363881584 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "general_project EP4CE6F17C8 " "Selected device EP4CE6F17C8 for design \"general_project\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1747363881596 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1747363881640 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1747363881640 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1747363881727 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1747363881727 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C8 " "Device EP4CE10F17C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1747363881966 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1747363881966 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1747363881966 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1747363881966 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3711 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1747363881966 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3713 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1747363881966 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3715 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1747363881966 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3717 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1747363881966 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1747363881966 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1747363881966 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "general_project.sdc " "Synopsys Design Constraints File file not found: 'general_project.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1747363882393 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1747363882393 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1747363882402 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1747363882402 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1747363882403 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1747363882479 ""}  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3707 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1747363882479 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN E15 (CLK4, DIFFCLK_2p)) " "Automatically promoted node rst_n~input (placed in PIN E15 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[0\]~0 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[0\]~0" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1454 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[1\]~1 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[1\]~1" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1455 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[2\]~2 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[2\]~2" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1456 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[3\]~3 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[3\]~3" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1457 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[4\]~4 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[4\]~4" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1458 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[5\]~5 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[5\]~5" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1459 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[0\]~3 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[0\]~3" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1463 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[1\]~7 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[1\]~7" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1467 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[2\]~11 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[2\]~11" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1471 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[3\]~15 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[3\]~15" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1475 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363882479 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" {  } {  } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1747363882479 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1747363882479 ""}  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3706 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1747363882479 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1747363882671 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1747363882671 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1747363882671 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1747363882671 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1747363882686 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1747363882686 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1747363882686 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1747363882686 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1747363882719 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1747363882719 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1747363882719 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363882750 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1747363882750 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1747363883087 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363883308 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1747363883322 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1747363885980 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363885980 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1747363886253 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "7 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" {  } { { "loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 1 { 0 "Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1747363886808 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1747363886808 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1747363887816 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1747363887816 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363887824 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.51 " "Total time spent on timing analysis during the Fitter is 0.51 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1747363887920 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1747363887935 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1747363888093 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1747363888093 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1747363888315 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363888699 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 Cyclone IV E " "4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rx_M2 3.3-V LVCMOS M2 " "Pin rx_M2 uses I/O standard 3.3-V LVCMOS at M2" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { rx_M2 } } } { "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rx_M2" } } } } { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 5 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 44 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1747363888878 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 2.5 V E15 " "Pin rst_n uses I/O standard 2.5 V at E15" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 43 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1747363888878 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk 2.5 V E1 " "Pin clk uses I/O standard 2.5 V at E1" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { clk } } } { "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1747363888878 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "key_F8 3.3-V LVCMOS F8 " "Pin key_F8 uses I/O standard 3.3-V LVCMOS at F8" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { key_F8 } } } { "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "key_F8" } } } } { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 47 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1747363888878 ""}  } {  } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1747363888878 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.fit.smsg " "Generated suppressed messages file C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1747363888952 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6507 " "Peak virtual memory: 6507 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1747363889333 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 16 10:51:29 2025 " "Processing ended: Fri May 16 10:51:29 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1747363889333 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1747363889333 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1747363889333 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1747363889333 ""}
