|general_project
clk => clk.IN3
rst_n => rst_n.IN3
rx_M2 => ~NO_FANOUT~
tx_G1 <= <GND>
SEL[0] <= LED_tube:LED_tube_1.SEL
SEL[1] <= LED_tube:LED_tube_1.SEL
SEL[2] <= LED_tube:LED_tube_1.SEL
SEL[3] <= LED_tube:LED_tube_1.SEL
SEL[4] <= LED_tube:LED_tube_1.SEL
SEL[5] <= LED_tube:LED_tube_1.SEL
DIG[0] <= LED_tube:LED_tube_1.DIG
DIG[1] <= LED_tube:LED_tube_1.DIG
DIG[2] <= LED_tube:LED_tube_1.DIG
DIG[3] <= LED_tube:LED_tube_1.DIG
DIG[4] <= LED_tube:LED_tube_1.DIG
DIG[5] <= LED_tube:LED_tube_1.DIG
DIG[6] <= LED_tube:LED_tube_1.DIG
DIG[7] <= LED_tube:LED_tube_1.DIG
matrix_K6 <= LED_matrix:LED_matrix_1.matrix_K6
key_F8 => key_F8.IN1
led[0] <= <GND>
led[1] <= <GND>
led[2] <= <GND>
led[3] <= <GND>


|general_project|LED_tube:LED_tube_1
clk => clk.IN2
rst_n => rst_n.IN2
num_to_display[0] => LessThan0.IN40
num_to_display[0] => Div0.IN33
num_to_display[0] => Mod0.IN33
num_to_display[0] => Mod1.IN26
num_to_display[1] => LessThan0.IN39
num_to_display[1] => Div0.IN32
num_to_display[1] => Mod0.IN32
num_to_display[1] => Mod1.IN25
num_to_display[2] => LessThan0.IN38
num_to_display[2] => Div0.IN31
num_to_display[2] => Mod0.IN31
num_to_display[2] => Mod1.IN24
num_to_display[3] => LessThan0.IN37
num_to_display[3] => Div0.IN30
num_to_display[3] => Mod0.IN30
num_to_display[3] => Mod1.IN23
num_to_display[4] => LessThan0.IN36
num_to_display[4] => Div0.IN29
num_to_display[4] => Mod0.IN29
num_to_display[4] => Mod1.IN22
num_to_display[5] => LessThan0.IN35
num_to_display[5] => Div0.IN28
num_to_display[5] => Mod0.IN28
num_to_display[5] => Mod1.IN21
num_to_display[6] => LessThan0.IN34
num_to_display[6] => Div0.IN27
num_to_display[6] => Mod0.IN27
num_to_display[6] => Mod1.IN20
num_to_display[7] => LessThan0.IN33
num_to_display[7] => Div0.IN26
num_to_display[7] => Mod0.IN26
num_to_display[7] => Mod1.IN19
num_to_display[8] => LessThan0.IN32
num_to_display[8] => Div0.IN25
num_to_display[8] => Mod0.IN25
num_to_display[8] => Mod1.IN18
num_to_display[9] => LessThan0.IN31
num_to_display[9] => Div0.IN24
num_to_display[9] => Mod0.IN24
num_to_display[9] => Mod1.IN17
num_to_display[10] => LessThan0.IN30
num_to_display[10] => Div0.IN23
num_to_display[10] => Mod0.IN23
num_to_display[10] => Mod1.IN16
num_to_display[11] => LessThan0.IN29
num_to_display[11] => Div0.IN22
num_to_display[11] => Mod0.IN22
num_to_display[11] => Mod1.IN15
num_to_display[12] => LessThan0.IN28
num_to_display[12] => Div0.IN21
num_to_display[12] => Mod0.IN21
num_to_display[12] => Mod1.IN14
num_to_display[13] => LessThan0.IN27
num_to_display[13] => Div0.IN20
num_to_display[13] => Mod0.IN20
num_to_display[13] => Mod1.IN13
num_to_display[14] => LessThan0.IN26
num_to_display[14] => Div0.IN19
num_to_display[14] => Mod0.IN19
num_to_display[14] => Mod1.IN12
num_to_display[15] => LessThan0.IN25
num_to_display[15] => Div0.IN18
num_to_display[15] => Mod0.IN18
num_to_display[15] => Mod1.IN11
num_to_display[16] => LessThan0.IN24
num_to_display[16] => Div0.IN17
num_to_display[16] => Mod0.IN17
num_to_display[16] => Mod1.IN10
num_to_display[17] => LessThan0.IN23
num_to_display[17] => Div0.IN16
num_to_display[17] => Mod0.IN16
num_to_display[17] => Mod1.IN9
num_to_display[18] => LessThan0.IN22
num_to_display[18] => Div0.IN15
num_to_display[18] => Mod0.IN15
num_to_display[18] => Mod1.IN8
num_to_display[19] => LessThan0.IN21
num_to_display[19] => Div0.IN14
num_to_display[19] => Mod0.IN14
num_to_display[19] => Mod1.IN7
SEL[0] <= tube_ctl:tube_ctl_1.SEL
SEL[1] <= tube_ctl:tube_ctl_1.SEL
SEL[2] <= tube_ctl:tube_ctl_1.SEL
SEL[3] <= tube_ctl:tube_ctl_1.SEL
SEL[4] <= tube_ctl:tube_ctl_1.SEL
SEL[5] <= tube_ctl:tube_ctl_1.SEL
DIG[0] <= tube_ctl:tube_ctl_1.DIG
DIG[1] <= tube_ctl:tube_ctl_1.DIG
DIG[2] <= tube_ctl:tube_ctl_1.DIG
DIG[3] <= tube_ctl:tube_ctl_1.DIG
DIG[4] <= tube_ctl:tube_ctl_1.DIG
DIG[5] <= tube_ctl:tube_ctl_1.DIG
DIG[6] <= tube_ctl:tube_ctl_1.DIG
DIG[7] <= tube_ctl:tube_ctl_1.DIG


|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1
clk => num_display[0]~reg0.CLK
clk => num_display[1]~reg0.CLK
clk => num_display[2]~reg0.CLK
clk => num_display[3]~reg0.CLK
clk => num_display[4]~reg0.CLK
clk => num_display[5]~reg0.CLK
clk => num_display[6]~reg0.CLK
clk => num_display[7]~reg0.CLK
clk => num_display[8]~reg0.CLK
clk => num_display[9]~reg0.CLK
clk => num_display[10]~reg0.CLK
clk => num_display[11]~reg0.CLK
clk => num_display[12]~reg0.CLK
clk => num_display[13]~reg0.CLK
clk => num_display[14]~reg0.CLK
clk => num_display[15]~reg0.CLK
clk => num_display[16]~reg0.CLK
clk => num_display[17]~reg0.CLK
clk => num_display[18]~reg0.CLK
clk => num_display[19]~reg0.CLK
clk => num_display[20]~reg0.CLK
clk => num_display[21]~reg0.CLK
clk => num_display[22]~reg0.CLK
clk => num_display[23]~reg0.CLK
clk => num_display[24]~reg0.CLK
clk => num_display[25]~reg0.CLK
clk => num_display[26]~reg0.CLK
clk => num_display[27]~reg0.CLK
clk => num_display[28]~reg0.CLK
clk => num_display[29]~reg0.CLK
clk => num_display[30]~reg0.CLK
clk => num_display[31]~reg0.CLK
clk => num_display[32]~reg0.CLK
clk => num_display[33]~reg0.CLK
clk => num_display[34]~reg0.CLK
clk => num_display[35]~reg0.CLK
clk => num_display[36]~reg0.CLK
clk => num_display[37]~reg0.CLK
clk => num_display[38]~reg0.CLK
clk => num_display[39]~reg0.CLK
clk => num_display[40]~reg0.CLK
clk => num_display[41]~reg0.CLK
clk => num_display[42]~reg0.CLK
clk => num_display[43]~reg0.CLK
clk => num_display[44]~reg0.CLK
clk => num_display[45]~reg0.CLK
clk => num_display[46]~reg0.CLK
clk => num_display[47]~reg0.CLK
clk => num_decode_6[0].CLK
clk => num_decode_6[1].CLK
clk => num_decode_6[2].CLK
clk => num_decode_6[3].CLK
clk => num_decode_6[4].CLK
clk => num_decode_6[5].CLK
clk => num_decode_6[6].CLK
clk => num_decode_6[7].CLK
clk => num_decode_5[0].CLK
clk => num_decode_5[1].CLK
clk => num_decode_5[2].CLK
clk => num_decode_5[3].CLK
clk => num_decode_5[4].CLK
clk => num_decode_5[5].CLK
clk => num_decode_5[6].CLK
clk => num_decode_5[7].CLK
clk => num_decode_4[0].CLK
clk => num_decode_4[1].CLK
clk => num_decode_4[2].CLK
clk => num_decode_4[3].CLK
clk => num_decode_4[4].CLK
clk => num_decode_4[5].CLK
clk => num_decode_4[6].CLK
clk => num_decode_4[7].CLK
clk => num_decode_3[0].CLK
clk => num_decode_3[1].CLK
clk => num_decode_3[2].CLK
clk => num_decode_3[3].CLK
clk => num_decode_3[4].CLK
clk => num_decode_3[5].CLK
clk => num_decode_3[6].CLK
clk => num_decode_3[7].CLK
clk => num_decode_2[0].CLK
clk => num_decode_2[1].CLK
clk => num_decode_2[2].CLK
clk => num_decode_2[3].CLK
clk => num_decode_2[4].CLK
clk => num_decode_2[5].CLK
clk => num_decode_2[6].CLK
clk => num_decode_2[7].CLK
clk => num_decode_1[0].CLK
clk => num_decode_1[1].CLK
clk => num_decode_1[2].CLK
clk => num_decode_1[3].CLK
clk => num_decode_1[4].CLK
clk => num_decode_1[5].CLK
clk => num_decode_1[6].CLK
clk => num_decode_1[7].CLK
rst_n => num_display[0]~reg0.PRESET
rst_n => num_display[1]~reg0.PRESET
rst_n => num_display[2]~reg0.PRESET
rst_n => num_display[3]~reg0.PRESET
rst_n => num_display[4]~reg0.PRESET
rst_n => num_display[5]~reg0.PRESET
rst_n => num_display[6]~reg0.PRESET
rst_n => num_display[7]~reg0.PRESET
rst_n => num_display[8]~reg0.PRESET
rst_n => num_display[9]~reg0.PRESET
rst_n => num_display[10]~reg0.PRESET
rst_n => num_display[11]~reg0.PRESET
rst_n => num_display[12]~reg0.PRESET
rst_n => num_display[13]~reg0.PRESET
rst_n => num_display[14]~reg0.PRESET
rst_n => num_display[15]~reg0.PRESET
rst_n => num_display[16]~reg0.PRESET
rst_n => num_display[17]~reg0.PRESET
rst_n => num_display[18]~reg0.PRESET
rst_n => num_display[19]~reg0.PRESET
rst_n => num_display[20]~reg0.PRESET
rst_n => num_display[21]~reg0.PRESET
rst_n => num_display[22]~reg0.PRESET
rst_n => num_display[23]~reg0.PRESET
rst_n => num_display[24]~reg0.PRESET
rst_n => num_display[25]~reg0.PRESET
rst_n => num_display[26]~reg0.PRESET
rst_n => num_display[27]~reg0.PRESET
rst_n => num_display[28]~reg0.PRESET
rst_n => num_display[29]~reg0.PRESET
rst_n => num_display[30]~reg0.PRESET
rst_n => num_display[31]~reg0.PRESET
rst_n => num_display[32]~reg0.PRESET
rst_n => num_display[33]~reg0.PRESET
rst_n => num_display[34]~reg0.PRESET
rst_n => num_display[35]~reg0.PRESET
rst_n => num_display[36]~reg0.PRESET
rst_n => num_display[37]~reg0.PRESET
rst_n => num_display[38]~reg0.PRESET
rst_n => num_display[39]~reg0.PRESET
rst_n => num_display[40]~reg0.PRESET
rst_n => num_display[41]~reg0.PRESET
rst_n => num_display[42]~reg0.PRESET
rst_n => num_display[43]~reg0.PRESET
rst_n => num_display[44]~reg0.PRESET
rst_n => num_display[45]~reg0.PRESET
rst_n => num_display[46]~reg0.PRESET
rst_n => num_display[47]~reg0.PRESET
rst_n => num_decode_6[0].PRESET
rst_n => num_decode_6[1].PRESET
rst_n => num_decode_6[2].PRESET
rst_n => num_decode_6[3].PRESET
rst_n => num_decode_6[4].ACLR
rst_n => num_decode_6[5].ACLR
rst_n => num_decode_6[6].ACLR
rst_n => num_decode_6[7].ACLR
rst_n => num_decode_5[0].PRESET
rst_n => num_decode_5[1].PRESET
rst_n => num_decode_5[2].PRESET
rst_n => num_decode_5[3].PRESET
rst_n => num_decode_5[4].ACLR
rst_n => num_decode_5[5].ACLR
rst_n => num_decode_5[6].ACLR
rst_n => num_decode_5[7].ACLR
rst_n => num_decode_4[0].PRESET
rst_n => num_decode_4[1].PRESET
rst_n => num_decode_4[2].PRESET
rst_n => num_decode_4[3].PRESET
rst_n => num_decode_4[4].ACLR
rst_n => num_decode_4[5].ACLR
rst_n => num_decode_4[6].ACLR
rst_n => num_decode_4[7].ACLR
rst_n => num_decode_3[0].PRESET
rst_n => num_decode_3[1].PRESET
rst_n => num_decode_3[2].PRESET
rst_n => num_decode_3[3].PRESET
rst_n => num_decode_3[4].ACLR
rst_n => num_decode_3[5].ACLR
rst_n => num_decode_3[6].ACLR
rst_n => num_decode_3[7].ACLR
rst_n => num_decode_2[0].PRESET
rst_n => num_decode_2[1].PRESET
rst_n => num_decode_2[2].PRESET
rst_n => num_decode_2[3].PRESET
rst_n => num_decode_2[4].ACLR
rst_n => num_decode_2[5].ACLR
rst_n => num_decode_2[6].ACLR
rst_n => num_decode_2[7].ACLR
rst_n => num_decode_1[0].PRESET
rst_n => num_decode_1[1].PRESET
rst_n => num_decode_1[2].PRESET
rst_n => num_decode_1[3].PRESET
rst_n => num_decode_1[4].ACLR
rst_n => num_decode_1[5].ACLR
rst_n => num_decode_1[6].ACLR
rst_n => num_decode_1[7].ACLR
numin_1[0] => Mod0.IN11
numin_1[0] => Div0.IN11
numin_1[1] => Mod0.IN10
numin_1[1] => Div0.IN10
numin_1[2] => Mod0.IN9
numin_1[2] => Div0.IN9
numin_1[3] => Mod0.IN8
numin_1[3] => Div0.IN8
numin_1[4] => Mod0.IN7
numin_1[4] => Div0.IN7
numin_1[5] => Mod0.IN6
numin_1[5] => Div0.IN6
numin_1[6] => Mod0.IN5
numin_1[6] => Div0.IN5
numin_1[7] => Mod0.IN4
numin_1[7] => Div0.IN4
numin_2[0] => Mod2.IN11
numin_2[0] => Div1.IN11
numin_2[1] => Mod2.IN10
numin_2[1] => Div1.IN10
numin_2[2] => Mod2.IN9
numin_2[2] => Div1.IN9
numin_2[3] => Mod2.IN8
numin_2[3] => Div1.IN8
numin_2[4] => Mod2.IN7
numin_2[4] => Div1.IN7
numin_2[5] => Mod2.IN6
numin_2[5] => Div1.IN6
numin_2[6] => Mod2.IN5
numin_2[6] => Div1.IN5
numin_2[7] => Mod2.IN4
numin_2[7] => Div1.IN4
numin_3[0] => Mod4.IN11
numin_3[0] => Div2.IN11
numin_3[1] => Mod4.IN10
numin_3[1] => Div2.IN10
numin_3[2] => Mod4.IN9
numin_3[2] => Div2.IN9
numin_3[3] => Mod4.IN8
numin_3[3] => Div2.IN8
numin_3[4] => Mod4.IN7
numin_3[4] => Div2.IN7
numin_3[5] => Mod4.IN6
numin_3[5] => Div2.IN6
numin_3[6] => Mod4.IN5
numin_3[6] => Div2.IN5
numin_3[7] => Mod4.IN4
numin_3[7] => Div2.IN4
num_display[0] <= num_display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[1] <= num_display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[2] <= num_display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[3] <= num_display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[4] <= num_display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[5] <= num_display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[6] <= num_display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[7] <= num_display[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[8] <= num_display[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[9] <= num_display[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[10] <= num_display[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[11] <= num_display[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[12] <= num_display[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[13] <= num_display[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[14] <= num_display[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[15] <= num_display[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[16] <= num_display[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[17] <= num_display[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[18] <= num_display[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[19] <= num_display[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[20] <= num_display[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[21] <= num_display[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[22] <= num_display[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[23] <= num_display[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[24] <= num_display[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[25] <= num_display[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[26] <= num_display[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[27] <= num_display[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[28] <= num_display[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[29] <= num_display[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[30] <= num_display[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[31] <= num_display[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[32] <= num_display[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[33] <= num_display[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[34] <= num_display[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[35] <= num_display[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[36] <= num_display[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[37] <= num_display[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[38] <= num_display[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[39] <= num_display[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[40] <= num_display[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[41] <= num_display[41]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[42] <= num_display[42]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[43] <= num_display[43]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[44] <= num_display[44]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[45] <= num_display[45]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[46] <= num_display[46]~reg0.DB_MAX_OUTPUT_PORT_TYPE
num_display[47] <= num_display[47]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|general_project|LED_tube:LED_tube_1|tube_ctl:tube_ctl_1
clk => cnt[0].CLK
clk => cnt[1].CLK
clk => cnt[2].CLK
clk => cnt[3].CLK
clk => cnt[4].CLK
clk => cnt[5].CLK
clk => cnt[6].CLK
clk => cnt[7].CLK
clk => cnt[8].CLK
clk => cnt[9].CLK
clk => cnt[10].CLK
clk => cnt[11].CLK
clk => cnt[12].CLK
clk => cnt[13].CLK
clk => cnt[14].CLK
clk => cnt[15].CLK
clk => cur_state~1.DATAIN
rst_n => SEL.OUTPUTSELECT
rst_n => SEL.OUTPUTSELECT
rst_n => SEL.OUTPUTSELECT
rst_n => SEL.OUTPUTSELECT
rst_n => SEL.OUTPUTSELECT
rst_n => SEL.OUTPUTSELECT
rst_n => DIG.OUTPUTSELECT
rst_n => DIG.OUTPUTSELECT
rst_n => DIG.OUTPUTSELECT
rst_n => DIG.OUTPUTSELECT
rst_n => DIG.OUTPUTSELECT
rst_n => DIG.OUTPUTSELECT
rst_n => DIG.OUTPUTSELECT
rst_n => DIG.OUTPUTSELECT
rst_n => next_state.s1.OUTPUTSELECT
rst_n => next_state.s2.OUTPUTSELECT
rst_n => next_state.s3.OUTPUTSELECT
rst_n => next_state.s4.OUTPUTSELECT
rst_n => next_state.s5.OUTPUTSELECT
rst_n => next_state.s6.OUTPUTSELECT
rst_n => cnt[0].ACLR
rst_n => cnt[1].ACLR
rst_n => cnt[2].ACLR
rst_n => cnt[3].ACLR
rst_n => cnt[4].ACLR
rst_n => cnt[5].ACLR
rst_n => cnt[6].ACLR
rst_n => cnt[7].ACLR
rst_n => cnt[8].ACLR
rst_n => cnt[9].ACLR
rst_n => cnt[10].ACLR
rst_n => cnt[11].ACLR
rst_n => cnt[12].ACLR
rst_n => cnt[13].ACLR
rst_n => cnt[14].ACLR
rst_n => cnt[15].ACLR
rst_n => cur_state~3.DATAIN
num_display[0] => Selector13.IN5
num_display[1] => Selector12.IN5
num_display[2] => Selector11.IN5
num_display[3] => Selector10.IN5
num_display[4] => Selector9.IN5
num_display[5] => Selector8.IN5
num_display[6] => Selector7.IN5
num_display[7] => Selector6.IN5
num_display[8] => Selector13.IN4
num_display[9] => Selector12.IN4
num_display[10] => Selector11.IN4
num_display[11] => Selector10.IN4
num_display[12] => Selector9.IN4
num_display[13] => Selector8.IN4
num_display[14] => Selector7.IN4
num_display[15] => Selector6.IN4
num_display[16] => Selector13.IN3
num_display[17] => Selector12.IN3
num_display[18] => Selector11.IN3
num_display[19] => Selector10.IN3
num_display[20] => Selector9.IN3
num_display[21] => Selector8.IN3
num_display[22] => Selector7.IN3
num_display[23] => Selector6.IN3
num_display[24] => Selector13.IN2
num_display[25] => Selector12.IN2
num_display[26] => Selector11.IN2
num_display[27] => Selector10.IN2
num_display[28] => Selector9.IN2
num_display[29] => Selector8.IN2
num_display[30] => Selector7.IN2
num_display[31] => Selector6.IN2
num_display[32] => Selector13.IN1
num_display[33] => Selector12.IN1
num_display[34] => Selector11.IN1
num_display[35] => Selector10.IN1
num_display[36] => Selector9.IN1
num_display[37] => Selector8.IN1
num_display[38] => Selector7.IN1
num_display[39] => Selector6.IN1
num_display[40] => Selector13.IN0
num_display[41] => Selector12.IN0
num_display[42] => Selector11.IN0
num_display[43] => Selector10.IN0
num_display[44] => Selector9.IN0
num_display[45] => Selector8.IN0
num_display[46] => Selector7.IN0
num_display[47] => Selector6.IN0
SEL[0] <= SEL.DB_MAX_OUTPUT_PORT_TYPE
SEL[1] <= SEL.DB_MAX_OUTPUT_PORT_TYPE
SEL[2] <= SEL.DB_MAX_OUTPUT_PORT_TYPE
SEL[3] <= SEL.DB_MAX_OUTPUT_PORT_TYPE
SEL[4] <= SEL.DB_MAX_OUTPUT_PORT_TYPE
SEL[5] <= SEL.DB_MAX_OUTPUT_PORT_TYPE
DIG[0] <= DIG.DB_MAX_OUTPUT_PORT_TYPE
DIG[1] <= DIG.DB_MAX_OUTPUT_PORT_TYPE
DIG[2] <= DIG.DB_MAX_OUTPUT_PORT_TYPE
DIG[3] <= DIG.DB_MAX_OUTPUT_PORT_TYPE
DIG[4] <= DIG.DB_MAX_OUTPUT_PORT_TYPE
DIG[5] <= DIG.DB_MAX_OUTPUT_PORT_TYPE
DIG[6] <= DIG.DB_MAX_OUTPUT_PORT_TYPE
DIG[7] <= DIG.DB_MAX_OUTPUT_PORT_TYPE


|general_project|LED_matrix:LED_matrix_1
clk => cnt_LED[0].CLK
clk => cnt_LED[1].CLK
clk => cnt_LED[2].CLK
clk => cnt_LED[3].CLK
clk => cnt_LED[4].CLK
clk => cnt_LED[5].CLK
clk => cnt_LED[6].CLK
clk => cnt_bit[0].CLK
clk => cnt_bit[1].CLK
clk => cnt_bit[2].CLK
clk => cnt_bit[3].CLK
clk => cnt_bit[4].CLK
clk => bit_index[0].CLK
clk => bit_index[1].CLK
clk => bit_index[2].CLK
clk => bit_index[3].CLK
clk => bit_index[4].CLK
clk => cnt[0].CLK
clk => cnt[1].CLK
clk => cnt[2].CLK
clk => cnt[3].CLK
clk => cnt[4].CLK
clk => cnt[5].CLK
clk => cnt[6].CLK
clk => cnt[7].CLK
clk => cnt[8].CLK
clk => cnt[9].CLK
clk => cnt[10].CLK
clk => cnt[11].CLK
clk => cnt[12].CLK
clk => cnt[13].CLK
clk => cnt[14].CLK
clk => cnt[15].CLK
clk => matrix_K6~reg0.CLK
clk => cur_state~1.DATAIN
rst_n => cnt_LED[0].ACLR
rst_n => cnt_LED[1].ACLR
rst_n => cnt_LED[2].ACLR
rst_n => cnt_LED[3].ACLR
rst_n => cnt_LED[4].ACLR
rst_n => cnt_LED[5].ACLR
rst_n => cnt_LED[6].ACLR
rst_n => cnt_bit[0].ACLR
rst_n => cnt_bit[1].ACLR
rst_n => cnt_bit[2].ACLR
rst_n => cnt_bit[3].ACLR
rst_n => cnt_bit[4].ACLR
rst_n => bit_index[0].PRESET
rst_n => bit_index[1].PRESET
rst_n => bit_index[2].PRESET
rst_n => bit_index[3].ACLR
rst_n => bit_index[4].PRESET
rst_n => cnt[0].ACLR
rst_n => cnt[1].ACLR
rst_n => cnt[2].ACLR
rst_n => cnt[3].ACLR
rst_n => cnt[4].ACLR
rst_n => cnt[5].ACLR
rst_n => cnt[6].ACLR
rst_n => cnt[7].ACLR
rst_n => cnt[8].ACLR
rst_n => cnt[9].ACLR
rst_n => cnt[10].ACLR
rst_n => cnt[11].ACLR
rst_n => cnt[12].ACLR
rst_n => cnt[13].ACLR
rst_n => cnt[14].ACLR
rst_n => cnt[15].ACLR
rst_n => matrix_K6~reg0.ACLR
rst_n => next_state.STOP.OUTPUTSELECT
rst_n => next_state.DELAY.OUTPUTSELECT
rst_n => next_state.IDLE.OUTPUTSELECT
rst_n => next_state.CHOOSE.OUTPUTSELECT
rst_n => next_state.SEND1.OUTPUTSELECT
rst_n => next_state.SEND0.OUTPUTSELECT
rst_n => data[20].OUTPUTSELECT
rst_n => data[18].OUTPUTSELECT
rst_n => data[17].OUTPUTSELECT
rst_n => data[11].OUTPUTSELECT
rst_n => data[10].OUTPUTSELECT
rst_n => data[9].OUTPUTSELECT
rst_n => data[8].OUTPUTSELECT
rst_n => data[4].OUTPUTSELECT
rst_n => data[1].OUTPUTSELECT
rst_n => cur_state~3.DATAIN
matrix_K6 <= matrix_K6~reg0.DB_MAX_OUTPUT_PORT_TYPE


|general_project|key_filter:key_filter_1
sys_clk => key_flag~reg0.CLK
sys_clk => cnt_20ms[0].CLK
sys_clk => cnt_20ms[1].CLK
sys_clk => cnt_20ms[2].CLK
sys_clk => cnt_20ms[3].CLK
sys_clk => cnt_20ms[4].CLK
sys_clk => cnt_20ms[5].CLK
sys_clk => cnt_20ms[6].CLK
sys_clk => cnt_20ms[7].CLK
sys_clk => cnt_20ms[8].CLK
sys_clk => cnt_20ms[9].CLK
sys_clk => cnt_20ms[10].CLK
sys_clk => cnt_20ms[11].CLK
sys_clk => cnt_20ms[12].CLK
sys_clk => cnt_20ms[13].CLK
sys_clk => cnt_20ms[14].CLK
sys_clk => cnt_20ms[15].CLK
sys_clk => cnt_20ms[16].CLK
sys_clk => cnt_20ms[17].CLK
sys_clk => cnt_20ms[18].CLK
sys_clk => cnt_20ms[19].CLK
sys_rst_n => cnt_20ms[0].ACLR
sys_rst_n => cnt_20ms[1].ACLR
sys_rst_n => cnt_20ms[2].ACLR
sys_rst_n => cnt_20ms[3].ACLR
sys_rst_n => cnt_20ms[4].ACLR
sys_rst_n => cnt_20ms[5].ACLR
sys_rst_n => cnt_20ms[6].ACLR
sys_rst_n => cnt_20ms[7].ACLR
sys_rst_n => cnt_20ms[8].ACLR
sys_rst_n => cnt_20ms[9].ACLR
sys_rst_n => cnt_20ms[10].ACLR
sys_rst_n => cnt_20ms[11].ACLR
sys_rst_n => cnt_20ms[12].ACLR
sys_rst_n => cnt_20ms[13].ACLR
sys_rst_n => cnt_20ms[14].ACLR
sys_rst_n => cnt_20ms[15].ACLR
sys_rst_n => cnt_20ms[16].ACLR
sys_rst_n => cnt_20ms[17].ACLR
sys_rst_n => cnt_20ms[18].ACLR
sys_rst_n => cnt_20ms[19].ACLR
sys_rst_n => key_flag~reg0.ACLR
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => cnt_20ms.OUTPUTSELECT
key_in => always0.IN1
key_flag <= key_flag~reg0.DB_MAX_OUTPUT_PORT_TYPE


