Analysis & Synthesis report for general_project
Fri May 16 10:51:20 2025
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. State Machine - |general_project|LED_matrix:LED_matrix_1|cur_state
  9. State Machine - |general_project|LED_tube:LED_tube_1|tube_ctl:tube_ctl_1|cur_state
 10. Registers Removed During Synthesis
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Parameter Settings for User Entity Instance: LED_tube:LED_tube_1|tube_ctl:tube_ctl_1
 15. Parameter Settings for User Entity Instance: LED_matrix:LED_matrix_1
 16. Parameter Settings for User Entity Instance: key_filter:key_filter_1
 17. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|lpm_divide:Div0
 18. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div2
 19. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod5
 20. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod4
 21. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|lpm_divide:Mod0
 22. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|lpm_divide:Div1
 23. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div1
 24. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod3
 25. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod2
 26. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|lpm_divide:Mod1
 27. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div0
 28. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod1
 29. Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod0
 30. Port Connectivity Checks: "LED_tube:LED_tube_1|num_tran:num_tran_1"
 31. Post-Synthesis Netlist Statistics for Top Partition
 32. Elapsed Time Per Partition
 33. Analysis & Synthesis Messages
 34. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2018  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri May 16 10:51:20 2025       ;
; Quartus Prime Version              ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
; Revision Name                      ; general_project                             ;
; Top-level Entity Name              ; general_project                             ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 1,642                                       ;
;     Total combinational functions  ; 1,613                                       ;
;     Dedicated logic registers      ; 189                                         ;
; Total registers                    ; 189                                         ;
; Total pins                         ; 24                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0                                           ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 0                                           ;
+------------------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                              ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option                                                           ; Setting            ; Default Value      ;
+------------------------------------------------------------------+--------------------+--------------------+
; Device                                                           ; EP4CE6F17C8        ;                    ;
; Top-level entity name                                            ; general_project    ; general_project    ;
; Family name                                                      ; Cyclone IV E       ; Cyclone V          ;
; Use smart compilation                                            ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                      ; Off                ; Off                ;
; Restructure Multiplexers                                         ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
; Preserve fewer node names                                        ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                         ; Auto               ; Auto               ;
; Safe State Machine                                               ; Off                ; Off                ;
; Extract Verilog State Machines                                   ; On                 ; On                 ;
; Extract VHDL State Machines                                      ; On                 ; On                 ;
; Ignore Verilog initial constructs                                ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
; Parallel Synthesis                                               ; On                 ; On                 ;
; DSP Block Balancing                                              ; Auto               ; Auto               ;
; NOT Gate Push-Back                                               ; On                 ; On                 ;
; Power-Up Don't Care                                              ; On                 ; On                 ;
; Remove Redundant Logic Cells                                     ; Off                ; Off                ;
; Remove Duplicate Registers                                       ; On                 ; On                 ;
; Ignore CARRY Buffers                                             ; Off                ; Off                ;
; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore LCELL Buffers                                             ; Off                ; Off                ;
; Ignore SOFT Buffers                                              ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
; Optimization Technique                                           ; Balanced           ; Balanced           ;
; Carry Chain Length                                               ; 70                 ; 70                 ;
; Auto Carry Chains                                                ; On                 ; On                 ;
; Auto Open-Drain Pins                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
; Auto ROM Replacement                                             ; On                 ; On                 ;
; Auto RAM Replacement                                             ; On                 ; On                 ;
; Auto DSP Block Replacement                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
; Strict RAM Replacement                                           ; Off                ; Off                ;
; Allow Synchronous Control Signals                                ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
; Auto RAM Block Balancing                                         ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                ; Off                ; Off                ;
; Auto Resource Sharing                                            ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                               ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                               ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                    ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
; Timing-Driven Synthesis                                          ; On                 ; On                 ;
; Report Parameter Settings                                        ; On                 ; On                 ;
; Report Source Assignments                                        ; On                 ; On                 ;
; Report Connectivity Checks                                       ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
; Clock MUX Protection                                             ; On                 ; On                 ;
; Auto Gated Clock Conversion                                      ; Off                ; Off                ;
; Block Design Naming                                              ; Auto               ; Auto               ;
; SDC constraint protection                                        ; Off                ; Off                ;
; Synthesis Effort                                                 ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                             ; Off                ; Off                ;
; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                           ; On                 ; On                 ;
+------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 16          ;
; Maximum allowed            ; 16          ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 16          ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.0%      ;
;     Processor 3            ;   0.0%      ;
;     Processor 4            ;   0.0%      ;
;     Processor 5            ;   0.0%      ;
;     Processor 6            ;   0.0%      ;
;     Processor 7            ;   0.0%      ;
;     Processor 8            ;   0.0%      ;
;     Processors 9-16        ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                               ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                           ; Library ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------+---------+
; ../rtl/tube_ctl.v                ; yes             ; User Verilog HDL File        ; C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v                               ;         ;
; ../rtl/num_tran.v                ; yes             ; User Verilog HDL File        ; C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v                               ;         ;
; ../rtl/LED_tube.v                ; yes             ; User Verilog HDL File        ; C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v                               ;         ;
; ../rtl/LED_matrix.v              ; yes             ; User Verilog HDL File        ; C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v                             ;         ;
; ../rtl/key_filter.v              ; yes             ; User Verilog HDL File        ; C:/DOCUMENT/fpga_projects/general_project/rtl/key_filter.v                             ;         ;
; ../rtl/general_project.v         ; yes             ; User Verilog HDL File        ; C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v                        ;         ;
; lpm_divide.tdf                   ; yes             ; Megafunction                 ; c:/application/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_divide.tdf      ;         ;
; abs_divider.inc                  ; yes             ; Megafunction                 ; c:/application/intelfpga_lite/18.1/quartus/libraries/megafunctions/abs_divider.inc     ;         ;
; sign_div_unsign.inc              ; yes             ; Megafunction                 ; c:/application/intelfpga_lite/18.1/quartus/libraries/megafunctions/sign_div_unsign.inc ;         ;
; aglobal181.inc                   ; yes             ; Megafunction                 ; c:/application/intelfpga_lite/18.1/quartus/libraries/megafunctions/aglobal181.inc      ;         ;
; db/lpm_divide_ekm.tdf            ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_ekm.tdf                    ;         ;
; db/sign_div_unsign_6nh.tdf       ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_6nh.tdf               ;         ;
; db/alt_u_div_0af.tdf             ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_0af.tdf                     ;         ;
; db/add_sub_7pc.tdf               ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/add_sub_7pc.tdf                       ;         ;
; db/add_sub_8pc.tdf               ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/add_sub_8pc.tdf                       ;         ;
; db/lpm_divide_jhm.tdf            ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_jhm.tdf                    ;         ;
; db/sign_div_unsign_bkh.tdf       ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_bkh.tdf               ;         ;
; db/alt_u_div_a4f.tdf             ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf                     ;         ;
; db/lpm_divide_m9m.tdf            ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_m9m.tdf                    ;         ;
; db/lpm_divide_hcm.tdf            ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_hcm.tdf                    ;         ;
; db/lpm_divide_3jm.tdf            ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_3jm.tdf                    ;         ;
; db/sign_div_unsign_rlh.tdf       ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_rlh.tdf               ;         ;
; db/alt_u_div_a7f.tdf             ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a7f.tdf                     ;         ;
; db/lpm_divide_3bm.tdf            ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_3bm.tdf                    ;         ;
; db/sign_div_unsign_olh.tdf       ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_olh.tdf               ;         ;
; db/alt_u_div_47f.tdf             ; yes             ; Auto-Generated Megafunction  ; C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_47f.tdf                     ;         ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------+---------+


+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary               ;
+---------------------------------------------+-------------+
; Resource                                    ; Usage       ;
+---------------------------------------------+-------------+
; Estimated Total logic elements              ; 1,642       ;
;                                             ;             ;
; Total combinational functions               ; 1613        ;
; Logic element usage by number of LUT inputs ;             ;
;     -- 4 input functions                    ; 458         ;
;     -- 3 input functions                    ; 379         ;
;     -- <=2 input functions                  ; 776         ;
;                                             ;             ;
; Logic elements by mode                      ;             ;
;     -- normal mode                          ; 1132        ;
;     -- arithmetic mode                      ; 481         ;
;                                             ;             ;
; Total registers                             ; 189         ;
;     -- Dedicated logic registers            ; 189         ;
;     -- I/O registers                        ; 0           ;
;                                             ;             ;
; I/O pins                                    ; 24          ;
;                                             ;             ;
; Embedded Multiplier 9-bit elements          ; 0           ;
;                                             ;             ;
; Maximum fan-out node                        ; rst_n~input ;
; Maximum fan-out                             ; 207         ;
; Total fan-out                               ; 5075        ;
; Average fan-out                             ; 2.74        ;
+---------------------------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node                   ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                      ; Entity Name         ; Library Name ;
+----------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+--------------+
; |general_project                             ; 1613 (21)           ; 189 (20)                  ; 0           ; 0            ; 0       ; 0         ; 24   ; 0            ; |general_project                                                                                                                                         ; general_project     ; work         ;
;    |LED_matrix:LED_matrix_1|                 ; 90 (90)             ; 40 (40)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_matrix:LED_matrix_1                                                                                                                 ; LED_matrix          ; work         ;
;    |LED_tube:LED_tube_1|                     ; 1474 (14)           ; 108 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1                                                                                                                     ; LED_tube            ; work         ;
;       |lpm_divide:Div0|                      ; 251 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Div0                                                                                                     ; lpm_divide          ; work         ;
;          |lpm_divide_ekm:auto_generated|     ; 251 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Div0|lpm_divide_ekm:auto_generated                                                                       ; lpm_divide_ekm      ; work         ;
;             |sign_div_unsign_6nh:divider|    ; 251 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Div0|lpm_divide_ekm:auto_generated|sign_div_unsign_6nh:divider                                           ; sign_div_unsign_6nh ; work         ;
;                |alt_u_div_0af:divider|       ; 251 (251)           ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Div0|lpm_divide_ekm:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_0af:divider                     ; alt_u_div_0af       ; work         ;
;       |lpm_divide:Div1|                      ; 151 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Div1                                                                                                     ; lpm_divide          ; work         ;
;          |lpm_divide_3jm:auto_generated|     ; 151 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Div1|lpm_divide_3jm:auto_generated                                                                       ; lpm_divide_3jm      ; work         ;
;             |sign_div_unsign_rlh:divider|    ; 151 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Div1|lpm_divide_3jm:auto_generated|sign_div_unsign_rlh:divider                                           ; sign_div_unsign_rlh ; work         ;
;                |alt_u_div_a7f:divider|       ; 151 (151)           ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Div1|lpm_divide_3jm:auto_generated|sign_div_unsign_rlh:divider|alt_u_div_a7f:divider                     ; alt_u_div_a7f       ; work         ;
;       |lpm_divide:Mod0|                      ; 277 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Mod0                                                                                                     ; lpm_divide          ; work         ;
;          |lpm_divide_hcm:auto_generated|     ; 277 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Mod0|lpm_divide_hcm:auto_generated                                                                       ; lpm_divide_hcm      ; work         ;
;             |sign_div_unsign_6nh:divider|    ; 277 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Mod0|lpm_divide_hcm:auto_generated|sign_div_unsign_6nh:divider                                           ; sign_div_unsign_6nh ; work         ;
;                |alt_u_div_0af:divider|       ; 277 (277)           ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Mod0|lpm_divide_hcm:auto_generated|sign_div_unsign_6nh:divider|alt_u_div_0af:divider                     ; alt_u_div_0af       ; work         ;
;       |lpm_divide:Mod1|                      ; 295 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Mod1                                                                                                     ; lpm_divide          ; work         ;
;          |lpm_divide_3bm:auto_generated|     ; 295 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Mod1|lpm_divide_3bm:auto_generated                                                                       ; lpm_divide_3bm      ; work         ;
;             |sign_div_unsign_olh:divider|    ; 295 (0)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Mod1|lpm_divide_3bm:auto_generated|sign_div_unsign_olh:divider                                           ; sign_div_unsign_olh ; work         ;
;                |alt_u_div_47f:divider|       ; 295 (295)           ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|lpm_divide:Mod1|lpm_divide_3bm:auto_generated|sign_div_unsign_olh:divider|alt_u_div_47f:divider                     ; alt_u_div_47f       ; work         ;
;       |num_tran:num_tran_1|                  ; 421 (61)            ; 86 (86)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1                                                                                                 ; num_tran            ; work         ;
;          |lpm_divide:Div0|                   ; 47 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div0                                                                                 ; lpm_divide          ; work         ;
;             |lpm_divide_jhm:auto_generated|  ; 47 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div0|lpm_divide_jhm:auto_generated                                                   ; lpm_divide_jhm      ; work         ;
;                |sign_div_unsign_bkh:divider| ; 47 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div0|lpm_divide_jhm:auto_generated|sign_div_unsign_bkh:divider                       ; sign_div_unsign_bkh ; work         ;
;                   |alt_u_div_a4f:divider|    ; 47 (47)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div0|lpm_divide_jhm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider ; alt_u_div_a4f       ; work         ;
;          |lpm_divide:Div1|                   ; 58 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div1                                                                                 ; lpm_divide          ; work         ;
;             |lpm_divide_jhm:auto_generated|  ; 58 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div1|lpm_divide_jhm:auto_generated                                                   ; lpm_divide_jhm      ; work         ;
;                |sign_div_unsign_bkh:divider| ; 58 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div1|lpm_divide_jhm:auto_generated|sign_div_unsign_bkh:divider                       ; sign_div_unsign_bkh ; work         ;
;                   |alt_u_div_a4f:divider|    ; 58 (58)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div1|lpm_divide_jhm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider ; alt_u_div_a4f       ; work         ;
;          |lpm_divide:Div2|                   ; 47 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div2                                                                                 ; lpm_divide          ; work         ;
;             |lpm_divide_jhm:auto_generated|  ; 47 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div2|lpm_divide_jhm:auto_generated                                                   ; lpm_divide_jhm      ; work         ;
;                |sign_div_unsign_bkh:divider| ; 47 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div2|lpm_divide_jhm:auto_generated|sign_div_unsign_bkh:divider                       ; sign_div_unsign_bkh ; work         ;
;                   |alt_u_div_a4f:divider|    ; 47 (47)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div2|lpm_divide_jhm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider ; alt_u_div_a4f       ; work         ;
;          |lpm_divide:Mod0|                   ; 52 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod0                                                                                 ; lpm_divide          ; work         ;
;             |lpm_divide_m9m:auto_generated|  ; 52 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod0|lpm_divide_m9m:auto_generated                                                   ; lpm_divide_m9m      ; work         ;
;                |sign_div_unsign_bkh:divider| ; 52 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod0|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider                       ; sign_div_unsign_bkh ; work         ;
;                   |alt_u_div_a4f:divider|    ; 52 (52)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod0|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider ; alt_u_div_a4f       ; work         ;
;          |lpm_divide:Mod1|                   ; 10 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod1                                                                                 ; lpm_divide          ; work         ;
;             |lpm_divide_m9m:auto_generated|  ; 10 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod1|lpm_divide_m9m:auto_generated                                                   ; lpm_divide_m9m      ; work         ;
;                |sign_div_unsign_bkh:divider| ; 10 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod1|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider                       ; sign_div_unsign_bkh ; work         ;
;                   |alt_u_div_a4f:divider|    ; 10 (10)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod1|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider ; alt_u_div_a4f       ; work         ;
;          |lpm_divide:Mod2|                   ; 63 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod2                                                                                 ; lpm_divide          ; work         ;
;             |lpm_divide_m9m:auto_generated|  ; 63 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod2|lpm_divide_m9m:auto_generated                                                   ; lpm_divide_m9m      ; work         ;
;                |sign_div_unsign_bkh:divider| ; 63 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod2|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider                       ; sign_div_unsign_bkh ; work         ;
;                   |alt_u_div_a4f:divider|    ; 63 (63)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod2|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider ; alt_u_div_a4f       ; work         ;
;          |lpm_divide:Mod3|                   ; 21 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod3                                                                                 ; lpm_divide          ; work         ;
;             |lpm_divide_m9m:auto_generated|  ; 21 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod3|lpm_divide_m9m:auto_generated                                                   ; lpm_divide_m9m      ; work         ;
;                |sign_div_unsign_bkh:divider| ; 21 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod3|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider                       ; sign_div_unsign_bkh ; work         ;
;                   |alt_u_div_a4f:divider|    ; 21 (21)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod3|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider ; alt_u_div_a4f       ; work         ;
;          |lpm_divide:Mod4|                   ; 52 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod4                                                                                 ; lpm_divide          ; work         ;
;             |lpm_divide_m9m:auto_generated|  ; 52 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod4|lpm_divide_m9m:auto_generated                                                   ; lpm_divide_m9m      ; work         ;
;                |sign_div_unsign_bkh:divider| ; 52 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod4|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider                       ; sign_div_unsign_bkh ; work         ;
;                   |alt_u_div_a4f:divider|    ; 52 (52)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod4|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider ; alt_u_div_a4f       ; work         ;
;          |lpm_divide:Mod5|                   ; 10 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod5                                                                                 ; lpm_divide          ; work         ;
;             |lpm_divide_m9m:auto_generated|  ; 10 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod5|lpm_divide_m9m:auto_generated                                                   ; lpm_divide_m9m      ; work         ;
;                |sign_div_unsign_bkh:divider| ; 10 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod5|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider                       ; sign_div_unsign_bkh ; work         ;
;                   |alt_u_div_a4f:divider|    ; 10 (10)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod5|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider ; alt_u_div_a4f       ; work         ;
;       |tube_ctl:tube_ctl_1|                  ; 65 (65)             ; 22 (22)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|LED_tube:LED_tube_1|tube_ctl:tube_ctl_1                                                                                                 ; tube_ctl            ; work         ;
;    |key_filter:key_filter_1|                 ; 28 (28)             ; 21 (21)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |general_project|key_filter:key_filter_1                                                                                                                 ; key_filter          ; work         ;
+----------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------+
; State Machine - |general_project|LED_matrix:LED_matrix_1|cur_state                                                          ;
+------------------+----------------+-----------------+-----------------+------------------+----------------+-----------------+
; Name             ; cur_state.STOP ; cur_state.SEND0 ; cur_state.SEND1 ; cur_state.CHOOSE ; cur_state.IDLE ; cur_state.DELAY ;
+------------------+----------------+-----------------+-----------------+------------------+----------------+-----------------+
; cur_state.DELAY  ; 0              ; 0               ; 0               ; 0                ; 0              ; 0               ;
; cur_state.STOP   ; 1              ; 0               ; 0               ; 0                ; 0              ; 1               ;
; cur_state.IDLE   ; 0              ; 0               ; 0               ; 0                ; 1              ; 1               ;
; cur_state.CHOOSE ; 0              ; 0               ; 0               ; 1                ; 0              ; 1               ;
; cur_state.SEND1  ; 0              ; 0               ; 1               ; 0                ; 0              ; 1               ;
; cur_state.SEND0  ; 0              ; 1               ; 0               ; 0                ; 0              ; 1               ;
+------------------+----------------+-----------------+-----------------+------------------+----------------+-----------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------+
; State Machine - |general_project|LED_tube:LED_tube_1|tube_ctl:tube_ctl_1|cur_state                     ;
+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
; Name         ; cur_state.s6 ; cur_state.s5 ; cur_state.s4 ; cur_state.s3 ; cur_state.s2 ; cur_state.s1 ;
+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
; cur_state.s1 ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
; cur_state.s2 ; 0            ; 0            ; 0            ; 0            ; 1            ; 1            ;
; cur_state.s3 ; 0            ; 0            ; 0            ; 1            ; 0            ; 1            ;
; cur_state.s4 ; 0            ; 0            ; 1            ; 0            ; 0            ; 1            ;
; cur_state.s5 ; 0            ; 1            ; 0            ; 0            ; 0            ; 1            ;
; cur_state.s6 ; 1            ; 0            ; 0            ; 0            ; 0            ; 1            ;
+--------------+--------------+--------------+--------------+--------------+--------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                       ;
+--------------------------------------------------------------------+---------------------------------------------------------------------+
; Register name                                                      ; Reason for Removal                                                  ;
+--------------------------------------------------------------------+---------------------------------------------------------------------+
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[7,23,31,39,47] ; Merged with LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[15] ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_2[7]            ; Merged with LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_1[7] ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_3[7]            ; Merged with LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_1[7] ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_4[7]            ; Merged with LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_1[7] ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_5[7]            ; Merged with LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_1[7] ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_6[7]            ; Merged with LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_1[7] ;
; LED_matrix:LED_matrix_1|cur_state~9                                ; Lost fanout                                                         ;
; Total Number of Removed Registers = 11                             ;                                                                     ;
+--------------------------------------------------------------------+---------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 189   ;
; Number of registers using Synchronous Clear  ; 41    ;
; Number of registers using Synchronous Load   ; 12    ;
; Number of registers using Asynchronous Clear ; 189   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 55    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------+
; Inverted Register Statistics                                      ;
+---------------------------------------------------------+---------+
; Inverted Register                                       ; Fan out ;
+---------------------------------------------------------+---------+
; LED_matrix:LED_matrix_1|bit_index[0]                    ; 5       ;
; LED_matrix:LED_matrix_1|bit_index[1]                    ; 5       ;
; LED_matrix:LED_matrix_1|bit_index[2]                    ; 4       ;
; LED_matrix:LED_matrix_1|bit_index[4]                    ; 3       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[40] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[32] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[24] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[16] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[0]  ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[8]  ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[41] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[33] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[25] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[17] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[1]  ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[9]  ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[42] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[34] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[26] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[18] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[2]  ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[10] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[43] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[35] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[27] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[19] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[3]  ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[11] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[44] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[36] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[28] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[20] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[4]  ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[12] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[45] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[37] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[29] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[21] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[5]  ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[13] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[46] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[38] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[30] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[22] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[6]  ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[14] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_display[15] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_6[0] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_5[0] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_4[0] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_3[0] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_1[0] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_2[0] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_6[1] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_5[1] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_4[1] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_3[1] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_1[1] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_2[1] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_6[2] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_5[2] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_4[2] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_3[2] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_1[2] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_2[2] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_6[3] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_5[3] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_4[3] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_3[3] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_1[3] ; 1       ;
; LED_tube:LED_tube_1|num_tran:num_tran_1|num_decode_2[3] ; 1       ;
; Total number of inverted registers = 71                 ;         ;
+---------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------+
; 3:1                ; 20 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |general_project|key_filter:key_filter_1|cnt_20ms[14]                  ;
; 4:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |general_project|LED_matrix:LED_matrix_1|bit_index[3]                  ;
; 5:1                ; 16 bits   ; 48 LEs        ; 16 LEs               ; 32 LEs                 ; Yes        ; |general_project|LED_matrix:LED_matrix_1|cnt[11]                       ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |general_project|LED_matrix:LED_matrix_1|bit_index[0]                  ;
; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |general_project|LED_tube:LED_tube_1|tube_ctl:tube_ctl_1|next_state.s6 ;
; 7:1                ; 7 bits    ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; No         ; |general_project|LED_tube:LED_tube_1|tube_ctl:tube_ctl_1|DIG[1]        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: LED_tube:LED_tube_1|tube_ctl:tube_ctl_1 ;
+----------------+--------+------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                       ;
+----------------+--------+------------------------------------------------------------+
; s1             ; 000001 ; Unsigned Binary                                            ;
; s2             ; 000010 ; Unsigned Binary                                            ;
; s3             ; 000100 ; Unsigned Binary                                            ;
; s4             ; 001000 ; Unsigned Binary                                            ;
; s5             ; 010000 ; Unsigned Binary                                            ;
; s6             ; 100000 ; Unsigned Binary                                            ;
+----------------+--------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: LED_matrix:LED_matrix_1 ;
+----------------+--------------------------+--------------------------+
; Parameter Name ; Value                    ; Type                     ;
+----------------+--------------------------+--------------------------+
; interval_frame ; 0011101010011000         ; Unsigned Binary          ;
; period         ; 111010                   ; Unsigned Binary          ;
; T0H            ; 001111                   ; Unsigned Binary          ;
; T0L            ; 101101                   ; Unsigned Binary          ;
; T1H            ; 011110                   ; Unsigned Binary          ;
; T1L            ; 011110                   ; Unsigned Binary          ;
; IDLE           ; 000010                   ; Unsigned Binary          ;
; CHOOSE         ; 000100                   ; Unsigned Binary          ;
; SEND1          ; 001000                   ; Unsigned Binary          ;
; SEND0          ; 010000                   ; Unsigned Binary          ;
; STOP           ; 000000                   ; Unsigned Binary          ;
; DELAY          ; 000001                   ; Unsigned Binary          ;
; YELLOW         ; 000001000000010000000000 ; Unsigned Binary          ;
; BLACK          ; 000100100000100100010010 ; Unsigned Binary          ;
; WHITE          ; 000000100000001000000010 ; Unsigned Binary          ;
; RED            ; 000000000000001000000000 ; Unsigned Binary          ;
+----------------+--------------------------+--------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: key_filter:key_filter_1 ;
+----------------+----------------------+------------------------------+
; Parameter Name ; Value                ; Type                         ;
+----------------+----------------------+------------------------------+
; CNT_MAX        ; 11110100001000111111 ; Unsigned Binary              ;
+----------------+----------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|lpm_divide:Div0 ;
+------------------------+----------------+--------------------------------------------+
; Parameter Name         ; Value          ; Type                                       ;
+------------------------+----------------+--------------------------------------------+
; LPM_WIDTHN             ; 20             ; Untyped                                    ;
; LPM_WIDTHD             ; 14             ; Untyped                                    ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                    ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                    ;
; LPM_PIPELINE           ; 0              ; Untyped                                    ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                    ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                    ;
; CBXI_PARAMETER         ; lpm_divide_ekm ; Untyped                                    ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                    ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                    ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                               ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                               ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                             ;
+------------------------+----------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div2 ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                                        ;
; LPM_WIDTHD             ; 4              ; Untyped                                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_jhm ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod5 ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                                        ;
; LPM_WIDTHD             ; 4              ; Untyped                                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_m9m ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod4 ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                                        ;
; LPM_WIDTHD             ; 4              ; Untyped                                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_m9m ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|lpm_divide:Mod0 ;
+------------------------+----------------+--------------------------------------------+
; Parameter Name         ; Value          ; Type                                       ;
+------------------------+----------------+--------------------------------------------+
; LPM_WIDTHN             ; 20             ; Untyped                                    ;
; LPM_WIDTHD             ; 14             ; Untyped                                    ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                    ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                    ;
; LPM_PIPELINE           ; 0              ; Untyped                                    ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                    ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                    ;
; CBXI_PARAMETER         ; lpm_divide_hcm ; Untyped                                    ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                    ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                    ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                               ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                               ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                             ;
+------------------------+----------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|lpm_divide:Div1 ;
+------------------------+----------------+--------------------------------------------+
; Parameter Name         ; Value          ; Type                                       ;
+------------------------+----------------+--------------------------------------------+
; LPM_WIDTHN             ; 14             ; Untyped                                    ;
; LPM_WIDTHD             ; 7              ; Untyped                                    ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                    ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                    ;
; LPM_PIPELINE           ; 0              ; Untyped                                    ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                    ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                    ;
; CBXI_PARAMETER         ; lpm_divide_3jm ; Untyped                                    ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                    ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                    ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                               ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                               ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                             ;
+------------------------+----------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div1 ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                                        ;
; LPM_WIDTHD             ; 4              ; Untyped                                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_jhm ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod3 ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                                        ;
; LPM_WIDTHD             ; 4              ; Untyped                                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_m9m ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod2 ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                                        ;
; LPM_WIDTHD             ; 4              ; Untyped                                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_m9m ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|lpm_divide:Mod1 ;
+------------------------+----------------+--------------------------------------------+
; Parameter Name         ; Value          ; Type                                       ;
+------------------------+----------------+--------------------------------------------+
; LPM_WIDTHN             ; 20             ; Untyped                                    ;
; LPM_WIDTHD             ; 7              ; Untyped                                    ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                    ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                    ;
; LPM_PIPELINE           ; 0              ; Untyped                                    ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                    ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                    ;
; CBXI_PARAMETER         ; lpm_divide_3bm ; Untyped                                    ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                    ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                    ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                               ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                               ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                             ;
+------------------------+----------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div0 ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                                        ;
; LPM_WIDTHD             ; 4              ; Untyped                                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_jhm ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod1 ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                                        ;
; LPM_WIDTHD             ; 4              ; Untyped                                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_m9m ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod0 ;
+------------------------+----------------+----------------------------------------------------------------+
; Parameter Name         ; Value          ; Type                                                           ;
+------------------------+----------------+----------------------------------------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                                                        ;
; LPM_WIDTHD             ; 4              ; Untyped                                                        ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                                                        ;
; LPM_PIPELINE           ; 0              ; Untyped                                                        ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                                        ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                                                        ;
; CBXI_PARAMETER         ; lpm_divide_m9m ; Untyped                                                        ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                                        ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                                        ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                                                 ;
+------------------------+----------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; Port Connectivity Checks: "LED_tube:LED_tube_1|num_tran:num_tran_1" ;
+------------+-------+----------+-------------------------------------+
; Port       ; Type  ; Severity ; Details                             ;
+------------+-------+----------+-------------------------------------+
; numin_1[7] ; Input ; Info     ; Stuck at GND                        ;
+------------+-------+----------+-------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 24                          ;
; cycloneiii_ff         ; 189                         ;
;     CLR               ; 111                         ;
;     CLR SCLR          ; 16                          ;
;     CLR SLD           ; 7                           ;
;     ENA CLR           ; 25                          ;
;     ENA CLR SCLR      ; 25                          ;
;     ENA CLR SLD       ; 5                           ;
; cycloneiii_lcell_comb ; 1613                        ;
;     arith             ; 481                         ;
;         1 data inputs ; 8                           ;
;         2 data inputs ; 125                         ;
;         3 data inputs ; 348                         ;
;     normal            ; 1132                        ;
;         0 data inputs ; 67                          ;
;         1 data inputs ; 30                          ;
;         2 data inputs ; 546                         ;
;         3 data inputs ; 31                          ;
;         4 data inputs ; 458                         ;
;                       ;                             ;
; Max LUT depth         ; 47.90                       ;
; Average LUT depth     ; 30.77                       ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:02     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Processing started: Fri May 16 10:51:08 2025
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off general_project -c general_project
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 16 of the 16 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/tx.v
    Info (12023): Found entity 1: tx File: C:/DOCUMENT/fpga_projects/general_project/rtl/tx.v Line: 4
Info (12021): Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/tube_ctl.v
    Info (12023): Found entity 1: tube_ctl File: C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/rx.v
    Info (12023): Found entity 1: rx File: C:/DOCUMENT/fpga_projects/general_project/rtl/rx.v Line: 4
Warning (10229): Verilog HDL Expression warning at num_tran.v(51): truncated literal to match 4 bits File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 51
Warning (10229): Verilog HDL Expression warning at num_tran.v(52): truncated literal to match 4 bits File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 52
Warning (10229): Verilog HDL Expression warning at num_tran.v(53): truncated literal to match 4 bits File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 53
Warning (10229): Verilog HDL Expression warning at num_tran.v(54): truncated literal to match 4 bits File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 54
Warning (10229): Verilog HDL Expression warning at num_tran.v(55): truncated literal to match 4 bits File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 55
Warning (10229): Verilog HDL Expression warning at num_tran.v(56): truncated literal to match 4 bits File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 56
Info (12021): Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/num_tran.v
    Info (12023): Found entity 1: num_tran File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/led_tube.v
    Info (12023): Found entity 1: LED_tube File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 2
Warning (10229): Verilog HDL Expression warning at LED_matrix.v(28): truncated literal to match 5 bits File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/led_matrix.v
    Info (12023): Found entity 1: LED_matrix File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/key_filter.v
    Info (12023): Found entity 1: key_filter File: C:/DOCUMENT/fpga_projects/general_project/rtl/key_filter.v Line: 20
Info (12021): Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/general_project.v
    Info (12023): Found entity 1: general_project File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 1
Info (12127): Elaborating entity "general_project" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at general_project.v(40): truncated value with size 32 to match size of target (20) File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 40
Warning (10034): Output port "led" at general_project.v(16) has no driver File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 16
Warning (10034): Output port "tx_G1" at general_project.v(6) has no driver File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 6
Info (12128): Elaborating entity "LED_tube" for hierarchy "LED_tube:LED_tube_1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 76
Warning (10230): Verilog HDL assignment warning at LED_tube.v(26): truncated value with size 32 to match size of target (8) File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 26
Warning (10230): Verilog HDL assignment warning at LED_tube.v(30): truncated value with size 32 to match size of target (8) File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 30
Warning (10230): Verilog HDL assignment warning at LED_tube.v(33): truncated value with size 32 to match size of target (8) File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 33
Info (12128): Elaborating entity "num_tran" for hierarchy "LED_tube:LED_tube_1|num_tran:num_tran_1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 52
Warning (10230): Verilog HDL assignment warning at num_tran.v(18): truncated value with size 32 to match size of target (4) File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 18
Warning (10230): Verilog HDL assignment warning at num_tran.v(19): truncated value with size 32 to match size of target (4) File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 19
Warning (10230): Verilog HDL assignment warning at num_tran.v(20): truncated value with size 32 to match size of target (4) File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 20
Warning (10230): Verilog HDL assignment warning at num_tran.v(21): truncated value with size 32 to match size of target (4) File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 21
Warning (10230): Verilog HDL assignment warning at num_tran.v(22): truncated value with size 32 to match size of target (4) File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 22
Warning (10230): Verilog HDL assignment warning at num_tran.v(23): truncated value with size 32 to match size of target (4) File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 23
Info (12128): Elaborating entity "tube_ctl" for hierarchy "LED_tube:LED_tube_1|tube_ctl:tube_ctl_1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 62
Info (12128): Elaborating entity "LED_matrix" for hierarchy "LED_matrix:LED_matrix_1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 84
Warning (10230): Verilog HDL assignment warning at LED_matrix.v(15): truncated value with size 32 to match size of target (16) File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v Line: 15
Warning (10230): Verilog HDL assignment warning at LED_matrix.v(17): truncated value with size 32 to match size of target (6) File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v Line: 17
Info (12128): Elaborating entity "key_filter" for hierarchy "key_filter:key_filter_1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 93
Info (278001): Inferred 13 megafunctions from design logic
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|Div0" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 26
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|num_tran:num_tran_1|Div2" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 23
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|num_tran:num_tran_1|Mod5" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 23
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|num_tran:num_tran_1|Mod4" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 22
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|Mod0" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 30
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|Div1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 30
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|num_tran:num_tran_1|Div1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 21
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|num_tran:num_tran_1|Mod3" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 21
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|num_tran:num_tran_1|Mod2" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 20
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|Mod1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 33
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|num_tran:num_tran_1|Div0" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 19
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|num_tran:num_tran_1|Mod1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 19
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "LED_tube:LED_tube_1|num_tran:num_tran_1|Mod0" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 18
Info (12130): Elaborated megafunction instantiation "LED_tube:LED_tube_1|lpm_divide:Div0" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 26
Info (12133): Instantiated megafunction "LED_tube:LED_tube_1|lpm_divide:Div0" with the following parameter: File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 26
    Info (12134): Parameter "LPM_WIDTHN" = "20"
    Info (12134): Parameter "LPM_WIDTHD" = "14"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_ekm.tdf
    Info (12023): Found entity 1: lpm_divide_ekm File: C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_ekm.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_6nh.tdf
    Info (12023): Found entity 1: sign_div_unsign_6nh File: C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_6nh.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_0af.tdf
    Info (12023): Found entity 1: alt_u_div_0af File: C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_0af.tdf Line: 26
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf
    Info (12023): Found entity 1: add_sub_7pc File: C:/DOCUMENT/fpga_projects/general_project/par/db/add_sub_7pc.tdf Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf
    Info (12023): Found entity 1: add_sub_8pc File: C:/DOCUMENT/fpga_projects/general_project/par/db/add_sub_8pc.tdf Line: 22
Info (12130): Elaborated megafunction instantiation "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div2" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 23
Info (12133): Instantiated megafunction "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div2" with the following parameter: File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 23
    Info (12134): Parameter "LPM_WIDTHN" = "8"
    Info (12134): Parameter "LPM_WIDTHD" = "4"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_jhm.tdf
    Info (12023): Found entity 1: lpm_divide_jhm File: C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_jhm.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf
    Info (12023): Found entity 1: sign_div_unsign_bkh File: C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_bkh.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_a4f.tdf
    Info (12023): Found entity 1: alt_u_div_a4f File: C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf Line: 26
Info (12130): Elaborated megafunction instantiation "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod5" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 23
Info (12133): Instantiated megafunction "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod5" with the following parameter: File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 23
    Info (12134): Parameter "LPM_WIDTHN" = "8"
    Info (12134): Parameter "LPM_WIDTHD" = "4"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_m9m.tdf
    Info (12023): Found entity 1: lpm_divide_m9m File: C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_m9m.tdf Line: 24
Info (12130): Elaborated megafunction instantiation "LED_tube:LED_tube_1|lpm_divide:Mod0" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 30
Info (12133): Instantiated megafunction "LED_tube:LED_tube_1|lpm_divide:Mod0" with the following parameter: File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 30
    Info (12134): Parameter "LPM_WIDTHN" = "20"
    Info (12134): Parameter "LPM_WIDTHD" = "14"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_hcm.tdf
    Info (12023): Found entity 1: lpm_divide_hcm File: C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_hcm.tdf Line: 24
Info (12130): Elaborated megafunction instantiation "LED_tube:LED_tube_1|lpm_divide:Div1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 30
Info (12133): Instantiated megafunction "LED_tube:LED_tube_1|lpm_divide:Div1" with the following parameter: File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 30
    Info (12134): Parameter "LPM_WIDTHN" = "14"
    Info (12134): Parameter "LPM_WIDTHD" = "7"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_3jm.tdf
    Info (12023): Found entity 1: lpm_divide_3jm File: C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_3jm.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_rlh.tdf
    Info (12023): Found entity 1: sign_div_unsign_rlh File: C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_rlh.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_a7f.tdf
    Info (12023): Found entity 1: alt_u_div_a7f File: C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a7f.tdf Line: 26
Info (12130): Elaborated megafunction instantiation "LED_tube:LED_tube_1|lpm_divide:Mod1" File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 33
Info (12133): Instantiated megafunction "LED_tube:LED_tube_1|lpm_divide:Mod1" with the following parameter: File: C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v Line: 33
    Info (12134): Parameter "LPM_WIDTHN" = "20"
    Info (12134): Parameter "LPM_WIDTHD" = "7"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_3bm.tdf
    Info (12023): Found entity 1: lpm_divide_3bm File: C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_3bm.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf
    Info (12023): Found entity 1: sign_div_unsign_olh File: C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_olh.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_47f.tdf
    Info (12023): Found entity 1: alt_u_div_47f File: C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_47f.tdf Line: 26
Info (12130): Elaborated megafunction instantiation "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div0" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 19
Info (12133): Instantiated megafunction "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Div0" with the following parameter: File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 19
    Info (12134): Parameter "LPM_WIDTHN" = "8"
    Info (12134): Parameter "LPM_WIDTHD" = "4"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12130): Elaborated megafunction instantiation "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod0" File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 18
Info (12133): Instantiated megafunction "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod0" with the following parameter: File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 18
    Info (12134): Parameter "LPM_WIDTHN" = "8"
    Info (12134): Parameter "LPM_WIDTHD" = "4"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (13000): Registers with preset signals will power-up high File: C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v Line: 73
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "tx_G1" is stuck at GND File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 6
    Warning (13410): Pin "led[0]" is stuck at GND File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 16
    Warning (13410): Pin "led[1]" is stuck at GND File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 16
    Warning (13410): Pin "led[2]" is stuck at GND File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 16
    Warning (13410): Pin "led[3]" is stuck at GND File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 16
Info (286030): Timing-Driven Synthesis is running
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
Info (17016): Found the following redundant logic cells in design
    Info (17048): Logic cell "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod5|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider|add_sub_7_result_int[0]~0" File: C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf Line: 61
    Info (17048): Logic cell "LED_tube:LED_tube_1|num_tran:num_tran_1|lpm_divide:Mod1|lpm_divide_m9m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_a4f:divider|add_sub_7_result_int[0]~0" File: C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf Line: 61
Info (144001): Generated suppressed messages file C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 1 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "rx_M2" File: C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v Line: 5
Info (21057): Implemented 1666 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 4 input pins
    Info (21059): Implemented 20 output pins
    Info (21061): Implemented 1642 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 30 warnings
    Info: Peak virtual memory: 4867 megabytes
    Info: Processing ended: Fri May 16 10:51:20 2025
    Info: Elapsed time: 00:00:12
    Info: Total CPU time (on all processors): 00:00:21


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.map.smsg.


