{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1747363722142 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1747363722142 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 16 10:48:42 2025 " "Processing started: Fri May 16 10:48:42 2025" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1747363722142 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363722142 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off general_project -c general_project " "Command: quartus_map --read_settings_files=on --write_settings_files=off general_project -c general_project" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363722142 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1747363722636 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1747363722636 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "start START tx.v(7) " "Verilog HDL Declaration information at tx.v(7): object \"start\" differs only in case from object \"START\" in the same scope" {  } { { "../rtl/tx.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tx.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747363731060 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx " "Found entity 1: tx" {  } { { "../rtl/tx.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tx.v" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731063 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731063 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/tube_ctl.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/tube_ctl.v" { { "Info" "ISGN_ENTITY_NAME" "1 tube_ctl " "Found entity 1: tube_ctl" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731065 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731065 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx " "Found entity 1: rx" {  } { { "../rtl/rx.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/rx.v" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731065 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731065 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(51) " "Verilog HDL Expression warning at num_tran.v(51): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 51 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363731065 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(52) " "Verilog HDL Expression warning at num_tran.v(52): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 52 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363731065 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(53) " "Verilog HDL Expression warning at num_tran.v(53): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 53 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363731065 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(54) " "Verilog HDL Expression warning at num_tran.v(54): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 54 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363731065 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(55) " "Verilog HDL Expression warning at num_tran.v(55): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 55 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363731065 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "4 num_tran.v(56) " "Verilog HDL Expression warning at num_tran.v(56): truncated literal to match 4 bits" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 56 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363731065 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/num_tran.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/num_tran.v" { { "Info" "ISGN_ENTITY_NAME" "1 num_tran " "Found entity 1: num_tran" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731065 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731065 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/led_tube.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/led_tube.v" { { "Info" "ISGN_ENTITY_NAME" "1 LED_tube " "Found entity 1: LED_tube" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731079 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731079 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "5 LED_matrix.v(28) " "Verilog HDL Expression warning at LED_matrix.v(28): truncated literal to match 5 bits" {  } { { "../rtl/LED_matrix.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v" 28 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747363731080 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/led_matrix.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/led_matrix.v" { { "Info" "ISGN_ENTITY_NAME" "1 LED_matrix " "Found entity 1: LED_matrix" {  } { { "../rtl/LED_matrix.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731080 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731080 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/key_filter.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/key_filter.v" { { "Info" "ISGN_ENTITY_NAME" "1 key_filter " "Found entity 1: key_filter" {  } { { "../rtl/key_filter.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/key_filter.v" 20 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731083 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731083 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/document/fpga_projects/general_project/rtl/general_project.v 1 1 " "Found 1 design units, including 1 entities, in source file /document/fpga_projects/general_project/rtl/general_project.v" { { "Info" "ISGN_ENTITY_NAME" "1 general_project " "Found entity 1: general_project" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731083 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731083 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "general_project " "Elaborating entity \"general_project\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1747363731190 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 general_project.v(40) " "Verilog HDL assignment warning at general_project.v(40): truncated value with size 32 to match size of target (20)" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731190 "|general_project"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 31 general_project.v(48) " "Verilog HDL assignment warning at general_project.v(48): truncated value with size 32 to match size of target (31)" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731190 "|general_project"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "led general_project.v(16) " "Output port \"led\" at general_project.v(16) has no driver" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1747363731200 "|general_project"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "tx_G1 general_project.v(6) " "Output port \"tx_G1\" at general_project.v(6) has no driver" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1747363731200 "|general_project"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED_tube LED_tube:LED_tube_1 " "Elaborating entity \"LED_tube\" for hierarchy \"LED_tube:LED_tube_1\"" {  } { { "../rtl/general_project.v" "LED_tube_1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363731214 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 LED_tube.v(26) " "Verilog HDL assignment warning at LED_tube.v(26): truncated value with size 32 to match size of target (8)" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731216 "|general_project|LED_tube:LED_tube_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 LED_tube.v(30) " "Verilog HDL assignment warning at LED_tube.v(30): truncated value with size 32 to match size of target (8)" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731216 "|general_project|LED_tube:LED_tube_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 LED_tube.v(33) " "Verilog HDL assignment warning at LED_tube.v(33): truncated value with size 32 to match size of target (8)" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731216 "|general_project|LED_tube:LED_tube_1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "num_tran LED_tube:LED_tube_1\|num_tran:num_tran_1 " "Elaborating entity \"num_tran\" for hierarchy \"LED_tube:LED_tube_1\|num_tran:num_tran_1\"" {  } { { "../rtl/LED_tube.v" "num_tran_1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 52 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363731218 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(18) " "Verilog HDL assignment warning at num_tran.v(18): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731220 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(19) " "Verilog HDL assignment warning at num_tran.v(19): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731220 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(20) " "Verilog HDL assignment warning at num_tran.v(20): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731220 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(21) " "Verilog HDL assignment warning at num_tran.v(21): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731220 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(22) " "Verilog HDL assignment warning at num_tran.v(22): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731220 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 num_tran.v(23) " "Verilog HDL assignment warning at num_tran.v(23): truncated value with size 32 to match size of target (4)" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731220 "|general_project|LED_tube:LED_tube_1|num_tran:num_tran_1"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tube_ctl LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1 " "Elaborating entity \"tube_ctl\" for hierarchy \"LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\"" {  } { { "../rtl/LED_tube.v" "tube_ctl_1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 62 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363731222 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED_matrix LED_matrix:LED_matrix_1 " "Elaborating entity \"LED_matrix\" for hierarchy \"LED_matrix:LED_matrix_1\"" {  } { { "../rtl/general_project.v" "LED_matrix_1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 91 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363731223 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 LED_matrix.v(15) " "Verilog HDL assignment warning at LED_matrix.v(15): truncated value with size 32 to match size of target (16)" {  } { { "../rtl/LED_matrix.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731223 "|general_project|LED_matrix:LED_matrix_1"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 LED_matrix.v(17) " "Verilog HDL assignment warning at LED_matrix.v(17): truncated value with size 32 to match size of target (6)" {  } { { "../rtl/LED_matrix.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_matrix.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1747363731223 "|general_project|LED_matrix:LED_matrix_1"}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "13 " "Inferred 13 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|Div0\"" {  } { { "../rtl/LED_tube.v" "Div0" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 26 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div2\"" {  } { { "../rtl/num_tran.v" "Div2" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod5 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod5\"" {  } { { "../rtl/num_tran.v" "Mod5" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod4 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod4\"" {  } { { "../rtl/num_tran.v" "Mod4" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 22 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|Mod0\"" {  } { { "../rtl/LED_tube.v" "Mod0" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|Div1\"" {  } { { "../rtl/LED_tube.v" "Div1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div1\"" {  } { { "../rtl/num_tran.v" "Div1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 21 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod3 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod3\"" {  } { { "../rtl/num_tran.v" "Mod3" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 21 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod2\"" {  } { { "../rtl/num_tran.v" "Mod2" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 20 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|Mod1\"" {  } { { "../rtl/LED_tube.v" "Mod1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 33 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Div0\"" {  } { { "../rtl/num_tran.v" "Div0" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod1\"" {  } { { "../rtl/num_tran.v" "Mod1" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|Mod0\"" {  } { { "../rtl/num_tran.v" "Mod0" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 18 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363731511 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1747363731511 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|lpm_divide:Div0\"" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 26 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363731568 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|lpm_divide:Div0 " "Instantiated megafunction \"LED_tube:LED_tube_1\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 20 " "Parameter \"LPM_WIDTHN\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731568 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 14 " "Parameter \"LPM_WIDTHD\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731568 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731568 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731568 ""}  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 26 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363731568 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ekm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ekm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ekm " "Found entity 1: lpm_divide_ekm" {  } { { "db/lpm_divide_ekm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_ekm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731625 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731625 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_6nh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_6nh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_6nh " "Found entity 1: sign_div_unsign_6nh" {  } { { "db/sign_div_unsign_6nh.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_6nh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731651 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731651 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_0af.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_0af.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_0af " "Found entity 1: alt_u_div_0af" {  } { { "db/alt_u_div_0af.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_0af.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731698 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731698 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7pc " "Found entity 1: add_sub_7pc" {  } { { "db/add_sub_7pc.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/add_sub_7pc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731750 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731750 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8pc " "Found entity 1: add_sub_8pc" {  } { { "db/add_sub_8pc.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/add_sub_8pc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731788 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731788 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div2 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div2\"" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363731805 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div2 " "Instantiated megafunction \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731805 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731805 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731805 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731805 ""}  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363731805 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_jhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_jhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_jhm " "Found entity 1: lpm_divide_jhm" {  } { { "db/lpm_divide_jhm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_jhm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731856 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731856 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_bkh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_bkh " "Found entity 1: sign_div_unsign_bkh" {  } { { "db/sign_div_unsign_bkh.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_bkh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731878 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731878 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_a4f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_a4f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_a4f " "Found entity 1: alt_u_div_a4f" {  } { { "db/alt_u_div_a4f.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731899 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731899 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5\"" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363731916 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5 " "Instantiated megafunction \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731916 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731916 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731916 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363731916 ""}  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 23 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363731916 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_m9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_m9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_m9m " "Found entity 1: lpm_divide_m9m" {  } { { "db/lpm_divide_m9m.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_m9m.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363731960 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363731960 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|lpm_divide:Mod0\"" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363732007 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|lpm_divide:Mod0 " "Instantiated megafunction \"LED_tube:LED_tube_1\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 20 " "Parameter \"LPM_WIDTHN\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732008 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 14 " "Parameter \"LPM_WIDTHD\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732008 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732008 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732008 ""}  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363732008 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_hcm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_hcm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_hcm " "Found entity 1: lpm_divide_hcm" {  } { { "db/lpm_divide_hcm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_hcm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363732057 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363732057 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|lpm_divide:Div1\"" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363732076 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|lpm_divide:Div1 " "Instantiated megafunction \"LED_tube:LED_tube_1\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 14 " "Parameter \"LPM_WIDTHN\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732076 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 7 " "Parameter \"LPM_WIDTHD\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732076 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732076 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732076 ""}  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 30 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363732076 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_3jm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_3jm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_3jm " "Found entity 1: lpm_divide_3jm" {  } { { "db/lpm_divide_3jm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_3jm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363732121 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363732121 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_rlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_rlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_rlh " "Found entity 1: sign_div_unsign_rlh" {  } { { "db/sign_div_unsign_rlh.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_rlh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363732145 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363732145 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_a7f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_a7f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_a7f " "Found entity 1: alt_u_div_a7f" {  } { { "db/alt_u_div_a7f.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a7f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363732173 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363732173 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|lpm_divide:Mod1 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|lpm_divide:Mod1\"" {  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 33 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363732241 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|lpm_divide:Mod1 " "Instantiated megafunction \"LED_tube:LED_tube_1\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 20 " "Parameter \"LPM_WIDTHN\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732241 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 7 " "Parameter \"LPM_WIDTHD\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732241 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732241 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732241 ""}  } { { "../rtl/LED_tube.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/LED_tube.v" 33 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363732241 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_3bm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_3bm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_3bm " "Found entity 1: lpm_divide_3bm" {  } { { "db/lpm_divide_3bm.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/lpm_divide_3bm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363732293 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363732293 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_olh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_olh " "Found entity 1: sign_div_unsign_olh" {  } { { "db/sign_div_unsign_olh.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/sign_div_unsign_olh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363732318 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363732318 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_47f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_47f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_47f " "Found entity 1: alt_u_div_47f" {  } { { "db/alt_u_div_47f.tdf" "" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_47f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747363732346 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363732346 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div0\"" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363732375 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div0 " "Instantiated megafunction \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732375 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732375 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732375 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732375 ""}  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 19 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363732375 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod0\"" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 18 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363732409 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod0 " "Instantiated megafunction \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732409 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732409 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732409 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1747363732409 ""}  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 18 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1747363732409 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 73 -1 0 } } { "../rtl/num_tran.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/num_tran.v" 59 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1747363732738 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1747363732738 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "tx_G1 GND " "Pin \"tx_G1\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363733670 "|general_project|tx_G1"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[0\] GND " "Pin \"led\[0\]\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363733670 "|general_project|led[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[1\] GND " "Pin \"led\[1\]\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363733670 "|general_project|led[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[2\] GND " "Pin \"led\[2\]\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363733670 "|general_project|led[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[3\] GND " "Pin \"led\[3\]\" is stuck at GND" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1747363733670 "|general_project|led[3]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1747363733670 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1747363733770 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1747363734326 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5\|lpm_divide_m9m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_a4f:divider\|add_sub_7_result_int\[0\]~0 " "Logic cell \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod5\|lpm_divide_m9m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_a4f:divider\|add_sub_7_result_int\[0\]~0\"" {  } { { "db/alt_u_div_a4f.tdf" "add_sub_7_result_int\[0\]~0" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf" 61 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363734340 ""} { "Info" "ISCL_SCL_CELL_NAME" "LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_a4f:divider\|add_sub_7_result_int\[0\]~0 " "Logic cell \"LED_tube:LED_tube_1\|num_tran:num_tran_1\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_bkh:divider\|alt_u_div_a4f:divider\|add_sub_7_result_int\[0\]~0\"" {  } { { "db/alt_u_div_a4f.tdf" "add_sub_7_result_int\[0\]~0" { Text "C:/DOCUMENT/fpga_projects/general_project/par/db/alt_u_div_a4f.tdf" 61 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363734340 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1747363734340 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.map.smsg " "Generated suppressed messages file C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363734378 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1747363734541 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747363734541 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_M2 " "No output dependent on input pin \"rx_M2\"" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 5 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363734650 "|general_project|rx_M2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key_F8 " "No output dependent on input pin \"key_F8\"" {  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 13 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1747363734650 "|general_project|key_F8"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1747363734650 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1692 " "Implemented 1692 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1747363734650 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1747363734650 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1668 " "Implemented 1668 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1747363734650 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1747363734650 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4866 " "Peak virtual memory: 4866 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1747363734675 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 16 10:48:54 2025 " "Processing ended: Fri May 16 10:48:54 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1747363734675 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1747363734675 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1747363734675 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1747363734675 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1747363735844 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1747363735858 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 16 10:48:55 2025 " "Processing started: Fri May 16 10:48:55 2025" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1747363735858 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1747363735858 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off general_project -c general_project " "Command: quartus_fit --read_settings_files=off --write_settings_files=off general_project -c general_project" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1747363735858 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1747363735992 ""}
{ "Info" "0" "" "Project  = general_project" {  } {  } 0 0 "Project  = general_project" 0 0 "Fitter" 0 0 1747363735992 ""}
{ "Info" "0" "" "Revision = general_project" {  } {  } 0 0 "Revision = general_project" 0 0 "Fitter" 0 0 1747363735992 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1747363736063 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1747363736071 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "general_project EP4CE6F17C8 " "Selected device EP4CE6F17C8 for design \"general_project\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1747363736081 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1747363736143 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1747363736143 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1747363736245 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1747363736251 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C8 " "Device EP4CE10F17C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1747363736507 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1747363736507 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1747363736507 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1747363736507 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3757 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1747363736507 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3759 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1747363736507 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3761 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1747363736507 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3763 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1747363736507 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1747363736507 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1747363736513 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "general_project.sdc " "Synopsys Design Constraints File file not found: 'general_project.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1747363736936 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1747363736936 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1747363736947 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1747363736947 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1747363736947 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1747363737027 ""}  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3754 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1747363737027 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN E15 (CLK4, DIFFCLK_2p)) " "Automatically promoted node rst_n~input (placed in PIN E15 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[0\]~0 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[0\]~0" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1463 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[1\]~1 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[1\]~1" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1464 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[2\]~2 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[2\]~2" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1465 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[3\]~3 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[3\]~3" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1466 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[4\]~4 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[4\]~4" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1467 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[5\]~5 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|SEL\[5\]~5" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 6 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1468 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[0\]~3 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[0\]~3" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1472 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[1\]~7 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[1\]~7" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1476 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[2\]~11 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[2\]~11" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1480 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[3\]~15 " "Destination node LED_tube:LED_tube_1\|tube_ctl:tube_ctl_1\|DIG\[3\]~15" {  } { { "../rtl/tube_ctl.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/tube_ctl.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 1484 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1747363737027 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" {  } {  } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1747363737027 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1747363737027 ""}  } { { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 3753 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1747363737027 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1747363737243 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1747363737243 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1747363737243 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1747363737243 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1747363737248 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1747363737248 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1747363737248 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1747363737248 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1747363737288 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1747363737288 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1747363737288 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363737322 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1747363737328 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1747363737720 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363737970 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1747363737980 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1747363740675 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363740675 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1747363740970 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "8 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 8% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" {  } { { "loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 1 { 0 "Router estimated peak interconnect usage is 8% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 12 { 0 ""} 11 12 12 13 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1747363741576 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1747363741576 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1747363742528 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1747363742528 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363742528 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.54 " "Total time spent on timing analysis during the Fitter is 0.54 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1747363742640 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1747363742657 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1747363742826 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1747363742826 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1747363743043 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1747363743466 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 Cyclone IV E " "4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rx_M2 3.3-V LVCMOS M2 " "Pin rx_M2 uses I/O standard 3.3-V LVCMOS at M2" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { rx_M2 } } } { "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rx_M2" } } } } { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 5 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 43 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1747363743687 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "key_F8 3.3-V LVCMOS F8 " "Pin key_F8 uses I/O standard 3.3-V LVCMOS at F8" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { key_F8 } } } { "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "key_F8" } } } } { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 46 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1747363743687 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 2.5 V E15 " "Pin rst_n uses I/O standard 2.5 V at E15" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1747363743687 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk 2.5 V E1 " "Pin clk uses I/O standard 2.5 V at E1" {  } { { "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/application/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { clk } } } { "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/application/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "../rtl/general_project.v" "" { Text "C:/DOCUMENT/fpga_projects/general_project/rtl/general_project.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "C:/DOCUMENT/fpga_projects/general_project/par/" { { 0 { 0 ""} 0 41 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1747363743687 ""}  } {  } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1747363743687 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.fit.smsg " "Generated suppressed messages file C:/DOCUMENT/fpga_projects/general_project/par/output_files/general_project.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1747363743760 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6509 " "Peak virtual memory: 6509 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1747363744192 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 16 10:49:04 2025 " "Processing ended: Fri May 16 10:49:04 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1747363744192 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1747363744192 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1747363744192 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1747363744192 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1747363745165 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1747363745169 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 16 10:49:05 2025 " "Processing started: Fri May 16 10:49:05 2025" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1747363745169 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1747363745169 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off general_project -c general_project " "Command: quartus_asm --read_settings_files=off --write_settings_files=off general_project -c general_project" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1747363745169 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1747363745477 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1747363745727 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1747363745740 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4677 " "Peak virtual memory: 4677 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1747363745861 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 16 10:49:05 2025 " "Processing ended: Fri May 16 10:49:05 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1747363745861 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1747363745861 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1747363745861 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1747363745861 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1747363746487 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1747363747005 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1747363747017 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 16 10:49:06 2025 " "Processing started: Fri May 16 10:49:06 2025" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1747363747017 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1747363747017 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta general_project -c general_project " "Command: quartus_sta general_project -c general_project" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1747363747017 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1747363747156 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1747363747431 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1747363747431 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363747474 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363747474 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "general_project.sdc " "Synopsys Design Constraints File file not found: 'general_project.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1747363747647 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363747647 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1747363747651 ""}  } {  } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1747363747651 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1747363747653 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1747363747653 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1747363747653 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1747363747665 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1747363747718 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1747363747718 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -55.731 " "Worst-case setup slack is -55.731" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363747723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363747723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -55.731           -2327.002 clk  " "  -55.731           -2327.002 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363747723 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363747723 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.453 " "Worst-case hold slack is 0.453" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363747728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363747728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.453               0.000 clk  " "    0.453               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363747728 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363747728 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1747363747735 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1747363747735 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363747744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363747744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000            -298.913 clk  " "   -3.000            -298.913 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363747744 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363747744 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363747813 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363747813 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363747813 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363747813 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 0.027 ns " "Worst Case Available Settling Time: 0.027 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363747813 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363747813 ""}  } {  } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1747363747813 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1747363747821 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1747363747825 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1747363748100 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1747363748205 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1747363748227 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1747363748227 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -50.883 " "Worst-case setup slack is -50.883" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748238 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748238 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -50.883           -2119.677 clk  " "  -50.883           -2119.677 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748238 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363748238 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.402 " "Worst-case hold slack is 0.402" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.402               0.000 clk  " "    0.402               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748251 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363748251 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1747363748256 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1747363748261 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000            -298.913 clk  " "   -3.000            -298.913 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748269 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363748269 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748335 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748335 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748335 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748335 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 0.117 ns " "Worst Case Available Settling Time: 0.117 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748335 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748335 ""}  } {  } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1747363748335 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1747363748346 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1747363748458 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1747363748458 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1747363748458 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -23.824 " "Worst-case setup slack is -23.824" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748470 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748470 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -23.824            -910.601 clk  " "  -23.824            -910.601 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748470 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363748470 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748472 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748472 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.186               0.000 clk  " "    0.186               0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748472 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363748472 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1747363748488 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1747363748495 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748502 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748502 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000            -214.884 clk  " "   -3.000            -214.884 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1747363748502 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1747363748502 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 0.582 ns " "Worst Case Available Settling Time: 0.582 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1747363748570 ""}  } {  } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1747363748570 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1747363748878 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1747363748878 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4914 " "Peak virtual memory: 4914 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1747363748956 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 16 10:49:08 2025 " "Processing ended: Fri May 16 10:49:08 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1747363748956 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1747363748956 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1747363748956 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1747363748956 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1747363750022 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1747363750027 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 16 10:49:09 2025 " "Processing started: Fri May 16 10:49:09 2025" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1747363750027 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1747363750027 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off general_project -c general_project " "Command: quartus_eda --read_settings_files=off --write_settings_files=off general_project -c general_project" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1747363750027 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1747363750666 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "general_project_8_1200mv_85c_slow.vo C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/ simulation " "Generated file general_project_8_1200mv_85c_slow.vo in folder \"C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1747363750923 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "general_project_8_1200mv_0c_slow.vo C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/ simulation " "Generated file general_project_8_1200mv_0c_slow.vo in folder \"C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1747363751076 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "general_project_min_1200mv_0c_fast.vo C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/ simulation " "Generated file general_project_min_1200mv_0c_fast.vo in folder \"C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1747363751223 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "general_project.vo C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/ simulation " "Generated file general_project.vo in folder \"C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1747363751358 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "general_project_8_1200mv_85c_v_slow.sdo C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/ simulation " "Generated file general_project_8_1200mv_85c_v_slow.sdo in folder \"C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1747363751473 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "general_project_8_1200mv_0c_v_slow.sdo C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/ simulation " "Generated file general_project_8_1200mv_0c_v_slow.sdo in folder \"C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1747363751577 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "general_project_min_1200mv_0c_v_fast.sdo C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/ simulation " "Generated file general_project_min_1200mv_0c_v_fast.sdo in folder \"C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1747363751690 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "general_project_v.sdo C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/ simulation " "Generated file general_project_v.sdo in folder \"C:/DOCUMENT/fpga_projects/general_project/par/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1747363751808 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4660 " "Peak virtual memory: 4660 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1747363751857 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 16 10:49:11 2025 " "Processing ended: Fri May 16 10:49:11 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1747363751857 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1747363751857 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1747363751857 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1747363751857 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 44 s " "Quartus Prime Full Compilation was successful. 0 errors, 44 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1747363752486 ""}
