moudule rx(
    input wire clk,
    input wire rst_n,
    input rx,
    
    output wire [7:0] data_rx,
    output wire done_rx
);

parameter [3:0] IDLE    = 4'b0001;
parameter [3:0] START   = 4'b0010;
parameter [3:0] DATA    = 4'b0100;
parameter [3:0] STOP    = 4'b1000;

reg [3:0] cur_state;
reg [3:0] next_state;
// 第一段
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        cur_state <= IDLE;
    else
        cur_state <= next_state;
end
// 第二段
always @(*) begin
    if(!rst_n)begin
        next_state <= IDLE;
    end
    else begin
        case (cur_state)
            IDLE    :begin
            
            end
            START   :begin
            
            end
            DATA    :begin
            
            end
            STOP    :begin
            
            end   
            defaut: next_state <= IDLE;        
        endcase
    end
end
// 第三段
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        cur_state <= IDLE;
    else
        cur_state <= next_state;
end